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path: root/drivers/spi
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2017-02-08dm: core: Replace of_offset with accessorSimon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-28ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz
This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
2017-01-15spi: Zap cf_qspi driver and related codeJagan Teki
Dropped becuase - driver not used any board. - no dm conversion. Cc: Angelo Dureghello <angelo@sysam.it> Cc: Richard Retanubun <richardretanubun@ruggedcom.com> Signed-off-by: Jagan Teki <jagan@openedev.com> Acked-by: Angelo Dureghello <angelo@sysam.it>
2017-01-13spi: Zap ep93xx_spi driver and related codeJagan Teki
Dropped becuase - driver and related configs not used any board. - no dm conversion. Cc: Heiko Schocher <hs@denx.de> Cc: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-04spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possibleVignesh R
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface reads until the last word of an indirect transfer So, make sure that QSPI indirect reads are 32 bit sized except for the final read. If the rxbuf is unaligned then use bounce buffer, so that readsl() can be used instead of readsb() to avoid non 32-bit accesses. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possibleVignesh R
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-21spi: Zap armada100_spi.c and envJagan Teki
armada100_spi.c and related env is zapping becuase of "no DM conversion". Cc: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
2016-12-21spi: Zap mpc52xx_spi.c, config and related codeJagan Teki
armada100_spi.c, related config options and related codes are zapping becuase of "no DM conversion". Cc: Werner Pfister <Pfister_Werner@intercontrol.de> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-15spi: cadence_qspi: Move DT prop code to match layoutPhil Edworthy
Move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Fix CS timingsPhil Edworthy
The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Remove returns from end of void functionsPhil Edworthy
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Use spi mode at the point it is neededPhil Edworthy
Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Clean up the #define namesPhil Edworthy
A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Use #define for bits instead of bit shiftsPhil Edworthy
Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Better debug information on the SPI clock ratePhil Edworthy
Show what the output clock rate actually is. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Fix baud rate calculationPhil Edworthy
With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: cadence_qspi: Fix clearing of pol/pha bitsPhil Edworthy
Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15spi: Add error checking for invalid bus widthsSimon Glass
At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-03ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XXNishanth Menon
CONFIG_AM57XX is just an unnecessary macro that is redundant given So, remove the same instead of spreading through out the u-boot source code and getting in the way to maintain common code for DRA7x family. Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-25spi: Add a debug() on bind failureSimon Glass
This is an uncommon error but we may as well have a debug() message when it happens. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-25rockchip: spi: Honour the deactivation delaySimon Glass
This is not currently implemented. Add support for this so that the Chrome OS EC can be used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-25rockchip: spi: Add support for of-platdataSimon Glass
Allow this driver to be used with of-platdata on rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-25spi: Add of-platdata support to SPI and SPI flashSimon Glass
Some boards may want to use these subsystems with of-platdata in SPL. Add support for this by avoiding any device tree access in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-18spi: kirkwood_spi: implement mvebu_spi_set_mode()Chris Packham
Set the appropriate bits in the interface config register based on the SPI_ mode flags. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Chris Packham <judge.packham@gmail.com>
2016-11-13spi: ti_qspi: Fix baudrate divider calculationVignesh R
Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-10-28dm: at91: Add driver model support for the spi driverWenyou Yang
Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-13libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass
The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
2016-10-12Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
2016-10-06Various, accumulated typos collected from around the tree.Robert P. J. Day
Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Stefan Roese <sr@denx.de>
2016-10-06spi: fsl_qspi: Preserve endianness of QSPI MCRYork Sun
The endianness can be changed by RCW + PBI sequence. It may have other than power on reset value. Signed-off-by: York Sun <york.sun@nxp.com> CC: Yuan Yao <yao.yuan@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Alison Wang <alison.wang@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-27spi: Add driver for Marvell Armada 3700 SoCStefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-23treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-22Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2016-09-22spi: Kconfig: Move FSL_QSPI entry to non-dm placeJagan Teki
Since FSL_QSPI driver still supporting non-dm code better to move the Kconfig from DM undefined place. Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: zynq: Use variable to remove u32 to u64 conversionsMichal Simek
Current code generates warning when it is compiled for arm64: Warnings: In file included from drivers/spi/zynq_spi.c:14:0: drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’: drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated to unsigned type [-Woverflow] writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’: drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly truncated to unsigned type [-Woverflow] writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ This patch is using one variable to do conversion via u32 variable. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: Use mode for rx mode flagsJagan Teki
Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: ti_qspi: Remove unnecessary udelay for AM437xVignesh R
This udelay() was added as an HACK and is no longer required. All read/write/erase operations work fine even without this delay. Hence, remove the udelay() call. Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: ti_qspi: use 128 bit transfer mode when writing to flashVignesh R
TI QSPI has four 32 bit data registers which can be used to transfer 16 bytes of data at once. The register group QSPI_SPI_DATA_REG_3, QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is treated as a single 128-bit word for shifting data in and out. The bit at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out in case of 128 bit transfer mode. Therefore the first byte to be written to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. Instead of writing 1 byte at a time when interacting with SPI NOR flash, make use of all the four registers so that 16 bytes can be transferred in one go. With this patch, the flash write speed increases from ~250KBs/ to ~650KB/s on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: zynq_spi: Fix infinite looping while xferLad, Prabhakar
During spi transfer, for example: sspi 1:1.0 8 ff the rx_len values will be: rx_len = 0 rx_len = 4294967295 This caused a busy looping during xfer, this patch fixes it by adding a check while reading the rx fifo Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-08-25spi: tegra: fix hang in set_mode()Stephen Warren
In tegra20_slink.c, the set_mode() function may be executed before the SPI bus is claimed the first time, and hence the clocks to the SPI controller may not be running. If so, any register read/write at this time will hang the CPU. Fix this by ensuring the clock is running as soon as the driver is probed. This is observed on the Tegra30 Beaver board. Apply the same clock initialization fix to all other Tegra SPI drivers so that if set_mode() is ever implemented there, the same bug will not appear. Note that tegra114_spi.c already operates in this fashion. The clock manipulation code is copied from claim_bus() to probe() rather than moved. This ensures that any calls to set_speed() take effect; the clock can't be set once during probe and left unchanged. Fixes: 5cb1b7b395c0 ("spi: tegra20: Add support for mode selection") Cc: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-07spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max valueChin Liang See
Ensuring the baudrate divisor value doesn't exceed the max value in the calculation.It will be capped at max value to ensure the correct value being written into the register. Example of the existing bug is when calculated div = 16. After and with the mask, the value written to register is actually 0 (register field for baudrate divisor). With this fix, the value written is now 15 which is max value for baudrate divisor. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jteki@openedev.com> Cc: Dinh Nguyen <dinguyen@altera.com>
2016-08-02driver: spi: fsl-qspi: remove compile WarningsYunhui Cui
Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-30spi: ti_qspi: dra7xx: Add support to use 76.8MHz clockVignesh R
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30spi: ti_qspi: Remove delay in read path for dra7xxVignesh R
As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30spi: ti_qspi: Fix compiler warning when DEBUG macro is setVignesh R
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30spi: ti_qspi: Fix failure on multiple READ_ID cmdVignesh R
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-27dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass
Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass
This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-09dm: spi: Read default speed and mode values from DTVignesh R
In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-09spi: cadence_quadspi: Enable QUAD mode based on DT dataVignesh R
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
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