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2019-05-08net: phy: Fix return value check phy_probeSiva Durga Prasad Paladugu
Don't ignore return value of phy_probe() call as the probe may fail and it needs to be reported. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08net: phy: Reloc next and prev pointers inside phy_driversSiva Durga Prasad Paladugu
This patch relocates the pointers inside phy_drivers incase of manual reloc. Without this reloc, these points to invalid pre relocation address and hence causes exception or hang. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08drivers: net: ldpaa_eth: fix resource leakPankaj Bansal
if an error occurs in ldpaa_eth_init, need to free all resources before returning the error. Threfore, free net_dev before returning from ldpaa_eth_init. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-07net: phy: realtek: Introduce quirk to mark RXC not stoppableCarlo Caione
When EEE is supported by the PHY and the driver allows it, libphy in the kernel is configuring the PHY to stop receiving the xMII clock while it is signaling LPI. While this (usually) works fine in the kernel this is causing issues in U-Boot when rebooting from the linux kernel with this bit set (without having the possibility to reset the PHY) where the PHY suddenly stops working. A new quirk is introduced to unconditionally reset this bit. If the quirk is not enabled using the proper configuration symbol, the PHY state is not changed. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-07net: phy: ti: use generic helpers to access MMD registersCarlo Caione
Now that generic helpers are available, use those instead of relying on ti specific functions. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-07net: phy: Add generic helpers to access MMD PHY registersCarlo Caione
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added to allow access to the MMD PHY registers. The MMD PHY registers can be accessed by several means: 1. Using two new MMD access function hooks in the PHY driver. These functions can be implemented when the PHY driver does not support the standard IEEE Compatible clause 45 access mechanism described in clause 22 or if the PHY uses its own non-standard access mechanism. 2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable DEVADs. 3. The standard clause 45 access extensions to the MMD registers through the indirection registers (clause 22) in all the other cases. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- RZ/A1 addition. - Old board removal.
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Assorted stratix10 fixes. - DDR driver DM migration.
2019-05-07spi: rpc: Add support for operation without clock frameworkMarek Vasut
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07net: sh_eth: Add support for operation without clock frameworkMarek Vasut
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07net: sh_eth: Add RZ/A1 supportMarek Vasut
Add support for RZ/A1 SoC specifics. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07serial: sh: Add RZ/A1 supportMarek Vasut
Add support for RZ/A1 SoC specifics. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07timer: renesas: Add RZ/A1 R7S72100 OSTM timer driverMarek Vasut
Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07pinctrl: renesas: Add RZ/A1 R7S72100 pin control driverMarek Vasut
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07gpio: renesas: Add RZ/A1 R7S72100 GPIO driverMarek Vasut
Add GPIO driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07sh: 7785: Remove CPU supportMarek Vasut
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-07sh: 7724: Remove CPU supportMarek Vasut
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various pinctrl / gpio fixes for R-Car
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Important spi-mem fix
2019-05-06arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-05usb: ohci: ohci-da8xx: Enable da850-ohci driver with DM supportAdam Ford
This patch reuses some former code for the hawkboard, combines it with some some similar DM_USB compatible code for the OHCI driver, and enables the use of the da850's OHCI controller with DM_USB compatibility. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-05dm: cache: add the pl310 cache controller driverDinh Nguyen
Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-05dm: cache: Create a uclass for cacheDinh Nguyen
The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-05-04Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mipsTom Rini
- mscc: small fixes, enhance network support for Serval, Luton and Ocelot - mt7620: rename arch to more generic name mtmips - mips: pass initrd addresses via DT as physical addresses
2019-05-04Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-bootTom Rini
2019-05-04net: ravb: Avoid unsupported internal delay mode for R-Car E3/D3Marek Vasut
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3 (r8a77995). Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM when the DT explicitly specifies RGMII ID or TXID mode instead of setting it unconditionally when the PHY link speed is 1000 Mbit/s. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-05-04pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()Marek Vasut
This function is now replaced by common pin controller GPIO configuration functionality, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04gpio: renesas: Migrate to pinctrl GPIO accessorsMarek Vasut
Switch to generic pin controller API for configuring pins as GPIOs instead of using the ad-hoc call into the R-Car PFC driver. Moreover, add .free() implementation for the GPIO controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Implement gpio_request_enable/gpio_disable_freeMarek Vasut
Implement the gpio_request_enable/gpio_disable_free callbacks to let the GPIO driver call the pin control framework and let it reconfigure pins as GPIOs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpioMarek Vasut
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin as a GPIO to retain the pin configuration information. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: gpio: Add callback for configuring pin as GPIOMarek Vasut
Add callback to configure, and de-configure, pin as a GPIO on the pin controller side. This matches similar functionality in Linux and aims to replace the ad-hoc implementations present in U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04Convert CONFIG_SUPPORT_EMMC_BOOT to KconfigAlex Kiernan
This converts the following to Kconfig: CONFIG_SUPPORT_EMMC_BOOT As requested by Michal Simek <michal.simek@xilinx.com>, these boards have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated: xilinx_zynqmp_zc1275_revB xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zcu100_revC xilinx_zynqmp_zcu102_rev1_0 xilinx_zynqmp_zcu102_revA xilinx_zynqmp_zcu102_revB xilinx_zynqmp_zcu104_revA xilinx_zynqmp_zcu104_revC xilinx_zynqmp_zcu106_revA xilinx_zynqmp_zcu111_revA Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2019-05-04usb: musb_hcd: remove unnecessary ifdefs for dm* SoCsBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped. The ifdefs in the musb_hcd driver are no longer needed. Remove them. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Marek Vasut <marex@denx.de>
2019-05-04nand: davinci: remove dead code for dm644xBartosz Golaszewski
The support for DaVinci DM* SoCs has been dropped. The code that used to be relevant to dm644x is no longer needed. Remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04net: davinci_emac: drop support for unused PHYsBartosz Golaszewski
The boards with SoCs from the DaVinci DM* family used to come with different PHYs that needed special support implemented in mach-davinci. Since the support for these chips has long been removed, we can now drop this unnused code from the emac driver. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-03Merge git://git.denx.de/u-boot-socfpgaTom Rini
- Misc MMC, FPGA bridge, general SoCFPGA fixes
2019-05-03Merge git://git.denx.de/u-boot-usbTom Rini
- DaVinci updates
2019-05-03Merge git://git.denx.de/u-boot-marvellTom Rini
- Fix in kwbimage (return code checking) (Young Xiao) - Misc updates to Turris Omnia (Marek)
2019-05-03usb: ohci: Re-enable commented out delayAdam Ford
There is a delay function that was commented out. This patch re-enables it, because it will be needed for da850 ohci support. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-03net: mscc: luton: Update network driver for pcb90Horatiu Vultur
Update Luton network driver to have support also for pcb90. The pcb90 has 24 ports from which 12 ports are connected to SerDes6G. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-05-03mips: rename mach-mt7620 to mach-mtmipsWeijie Gao
Currently mach-mt7620 contains only support for mt7628. To avoid confusion, rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms. MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628 because they do not share the same lowlevel codes. Dependencies of four drivers are changed to SOC_MT7628 as these drivers are only used by MT7628. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-05-03net: mscc: ocelot: Update network driver for pcb120Horatiu Vultur
Update Ocelot network driver to have support also for pcb120. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-05-03net: Add MSCC Serval network driver.Horatiu Vultur
Add network driver for Microsemi Ethernet switch. It is present on Serval SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-05-03mmc: sdhci: Add Support for ADMA2Faiz Abbas
The Standard Host Controller Interface (SDHCI) specification version 3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths of DMA. ADMA2 uses a table of descriptors for aggregating DMA requests. This significantly improves read and write throughput. Add Support for the same. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-05-03mmc: sdhci: Move DMA handling to prepare_dma() functionFaiz Abbas
In preparation for addition of ADMA2 support, cleanup SDMA handling by moving it to a new sdhci_prepare_dma() function. Also add a flags field in sdhci_host to indicate if DMA is enabled. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-05-03mmc: fsl_esdhc: Fix wp_enable issueYe Li
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed to gpio function, can't be used as internal WP checking. However the codes remain to use internal WP checking. This patch changes to examine the "fsl,wp-controller" for enabling internal WP checking, and "wp-gpios" for muxing to gpio. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-05-03mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issueYe Li
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2019-05-03Merge branch '2019-05-03-master-imports'Tom Rini
- Various btrfs fixes - Various TI platform fixes - Other fixes (cross build, taurus update, Kconfig help text)
2019-05-03firmware: ti_sci: Always request response from firmwareAndrew F. Davis
TI-SCI firmware will only respond to messages when the TI_SCI_FLAG_REQ_ACK_ON_PROCESSED flag is set. Most messages already do this, set this for the ones that do not. Signed-off-by: Andrew F. Davis <afd@ti.com> Tested-by: Alejandro Hernandez <ajhernandez@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
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