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2019-04-22mtd: nand: provide several helpers to do common NAND operationsBoris Brezillon
Linux commit 97d90da8a88 ("mtd: nand: provide several helpers to do common NAND operations") This is part of the process of removing direct calls to ->cmdfunc() outside of the core in order to introduce a better interface to execute NAND operations. Here we provide several helpers and make use of them to remove all direct calls to ->cmdfunc(). This way, we can easily modify those helpers to make use of the new ->exec_op() interface when available. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [miquel.raynal@free-electrons.com: rebased and fixed some conflicts] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> [Philippe Reynes: adapt code to u-boot and only keep new function] Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-21Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- Various fastboot, dwc2/stm32 updates
2019-04-21Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Various stratix10, gen5 updates
2019-04-21usb: dwc2: fix gadget disconnectFabrice Gasnier
This fixes a disconnect issue detected with fastboot command, when using dwc2 driver. - On u-boot side: uboot>$ fastboot 0 - On USB host PC side, few seconds after PC>$ fastboot reboot # Get stuck, uboot target never reboots By enabling DEBUG_ISR logs, the bus suspend interrupt is seen before the PC command has been issued. When the USB bus suspend occurs, there's a HACK that disables the fastboot (composite driver). Here is the call stack upon USB bus suspend: - dwc2_handle_usb_suspend_intr() - dev->driver->disconnect() - composite_disconnect() - reset_config() - f->disable() - fastboot_disable() - usb_ep_disable(f_fb->out_ep); - usb_ep_disable(f_fb->in_ep); .. other disable calls. When the resume interrupt happens, everything has been disabled, then nothing happens. fastboot command gets stuck on HOST side. Remove original HACK, that disconnects the composite driver upon USB bus suspend. Implement disconnect detection instead: - check GINTSTS OTG interrupt - read GOTGINT register - check GOTGINT, SesEndDet bit (e.g. session end) This is inspired by what is implemented currently in Linux dwc2 driver. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-04-21fastboot: add support for 'getvar platform'Eugeniu Rosca
Our R-Car3 Android userspace relies on the output of 'fastboot getvar platform' and U-Boot currently is not able to handle it: host $> fastboot getvar platform getvar:platform FAILED (remote: Variable not implemented) finished. total time: 0.001s We either have the option of adding 'fastboot.platform' variable to the default/saved environment as a workaround or add proper 'fastboot getvar platform' support in U-Boot via this patch. In the latter case, other platforms can benefit from it too. Note that R-Car3 already exports 'platform' environment variable via v2019.01 commit 00e4b57e9e71c3 ("ARM: rmobile: Set environment variable containing CPU type"). Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-04-21fastboot: Replace literal 32 with PART_NAME_LENAlex Kiernan
Where we have to compute partition names, rather than using a hardcoded 32 for the partition name length, replace with PART_NAME_LEN. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
2019-04-21stm32mp1: add stusb1600 support for DK1 and DK2 boardPatrick Delaunay
The DK1 and DK2 boards use the USB Type-C controller STUSB1600. This patch updates: - the device tree to add the I2C node in the DT - the board stm32mp1 to probe this I2C device and use this controller to check cable detection. - the DWC2 driver to support a new dt property "u-boot,force-b-session-valid" which forces B session and device mode; it is a workaround because the VBUS sensing and ID detection isn't available with stusb1600. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: add support for STM32MP1Patrick Delaunay
Add compatible "st,stm32mp1-hsotg" and associated driver data to manage the usb33d-supply and the ST specific register for VBus sensing. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> # Conflicts: # drivers/usb/gadget/dwc2_udc_otg.c Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2_udc_otg: Add tx_fifo_sz array supportPatrice Chotard
All TX fifo size can be different, add tx_fifo_sz_array[] into dwc2_plat_otg_data to be able to set them. tx_fifo_sz_array[] is 17 Bytes long and can contains max 16 tx fifo size (synopsys IP supports max 16 IN endpoints). First entry of tx_fifo_sz_array[] is the number of valid fifo size the array contains. In case of tx_fifo_sz_array[] doesn't contains the same number of element than max hardware endpoint, display a warning message. Compatibility with board which doesn't use tx_fifo_sz_array[] (Rockchip rk322x/rk3128/rv1108/rk3288/rk3036) is kept. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2_udc_otg: Read MAX_HW_ENDPOINT from HWCFG4 registerPatrick Delaunay
Some DWC2 ip variant doesn't use 16 hardware endpoint as hardcoded in the driver. Bits INEps [29:26] of HWCFG4 register allows to get this information. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: Add function for session B checkPatrick Delaunay
Add a new function to check the session B validity, to be use to check cable connection. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: Add force-b-session-valid supportPatrick Delaunay
Handle "force-b-session-valid" property from DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: force reset assert before to probe the driverPatrick Delaunay
Reset the hardware to be sure of the device state. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: convert driver to DM_USB_GADGETPatrick Delaunay
Minimal conversion to driver model by using the uclass UCLASS_USB_GADGET_GENERIC based on: - reset uclass - clock uclass - generic uclass. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21usb: dwc2: remove unused variable regs_otgPatrick Delaunay
Remove the global regs_otg variable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-21phy: usbphyc: increase PLL wait timeoutPatrick Delaunay
wait 200us to solve USB init issue on device mode (ums and stm32prog commands) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: move vdda1v1 and vdda1v8 in phy_initPatrick Delaunay
vdda1v1 and vdda1v8 are used by the PLL. Both need to be enabled before starting the PLL. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: Binding update of vdda supplyPatrick Delaunay
Move supply vdda1v1 and vdda1v8 in usbphyc node and no more in port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: update xlate with DT bindingPatrick Delaunay
Parameter added for port 1, for example: &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb"; vbus-supply = <&vbus_sw>; status = "okay"; }; &usbotg_hs { pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a>; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; }; Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21phy: usbphyc: remove unused variable indexPatrick Delaunay
Remove unused field index in struct stm32_usbphyc_phy. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21fastboot: Improve error reporting on 'getvar partition-{size, type}'Eugeniu Rosca
Currently U-Boot reports the same error message in all below cases: [A] host> fastboot getvar partition-type [B] host> fastboot getvar partition-size [C] host> fastboot getvar partition-type: [D] host> fastboot getvar partition-size: [E] host> fastboot getvar partition-type:<invalid-part> [F] host> fastboot getvar partition-size:<invalid-part> The message looks like: host> fastboot getvar partition-size: getvar:partition-size: FAILED (remote: partition not found) Finished. Total time: 0.003s Be more user friendly and output: - "partition not given" for [A-D] - "partition not found" for [E-F] Fixes: f73a7df984a9 ("net: fastboot: Merge AOSP UDP fastboot") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> Acked-by: Alex Kiernan <alex.kiernan@gmail.com>
2019-04-21fastboot: getvar: correct/rename "has_slot" to "has-slot"Eugeniu Rosca
Since its inception in upstream fastboot android-n-preview-1 [1], "has-slot" option has never taken the form of "has_slot". Amongst the users of "getvar has-slot:" is the upstream bootloadertest.py [2]. Current U-Boot "has_slot" version must be a typo. Fix it. [1] https://android.googlesource.com/platform/system/core/+/a797479bd51c ("Fix fastboot variable name") [2] https://android.googlesource.com/platform/system/extras/+/72de393e118e3 ("Bootloader verification for AndroidThings.") Fixes: f73a7df984a9 ("net: fastboot: Merge AOSP UDP fastboot") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> Acked-by: Alex Kiernan <alex.kiernan@gmail.com>
2019-04-19usb: Select USB_MUSB_DSPS with USB_MUSB_TIAlex Kiernan
USB_MUSB_TI requires USB_MUSB_DSPS, failing at link time if it's not selected: drivers/usb/musb-new/built-in.o: In function `ti_musb_host_ofdata_to_platdata': drivers/usb/musb-new/ti-musb.c:193: undefined reference to `musb_dsps_ops' or if OF_CONTROL is not selected: arch/arm/mach-omap2/built-in.o:(.data.usb0+0x24): undefined reference to `musb_dsps_ops' Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at> Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2019-04-19configs: Migrate USB_MUSB_DISABLE_BULK_COMBINE_SPLIT to KconfigAlex Kiernan
Migrate support for disable MUSB bulk split/combine to Kconfig Green Travis build: https://travis-ci.org/akiernan/u-boot/builds/519101867 Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2019-04-18Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arcTom Rini
In this small series we migrate ARC boards to DM_MMC so we're hopefully are good now and our boards will be kept in U-Boot for some more time :)
2019-04-18ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboardsEugeniy Paltsev
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys ARC devboards. It is created to switch ARC devboards to use DM_MMC. It required information such as clocks (Bus Interface Unit clock, Card Interface Unit clock) and SDIO bus width. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-04-17timer: dw-apb: Add missing 64bit up-conversionMarek Vasut
The generic timer count is an incrementing 64bit value and a timer driver must return an incrementing 64bit value. The DW APB timer only provides a 32bit timer counting down, thus the result must be inverted and converted to a 64bit value. The current implementation is however missing the 64bit up-conversion and this results in random timer roll-overs, which in turn triggers random timeouts throughout the codebase. This patch adds the missing 64bit up-conversion to fix the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-17ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan
Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan
Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan
Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17spi: cadence_qspi: add reset handlingSimon Goldschmidt
This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17mtd: rawnand: denali: add reset handlingSimon Goldschmidt
This adds reset handling to the devicetree-enabled Denali NAND driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt
To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17reset: socfpga: add reset handling for old kernelsSimon Goldschmidt
This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL. However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround. This workaround is implemented in the 'assert' and 'remove' callbacks of this reset driver: the 'assert' callback does not disable peripherals that were already taken out of reset, while the 'remove' callback, which is called on OS_PREPARE, deasserts all peripheral resets if the environment variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5 SPL did up to now. This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17reset: socfpga: rename membase ptr to modrst_baseSimon Goldschmidt
The only member of this driver's priv struct is a pointer, which is called 'membase'. However, since this driver handles multiple sub- architectures, this is not the base address from dts but the base address of some common registers of those sub-arches. Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- drop non-DM code from ti_qspi - support spi-mem for ti_qspi
2019-04-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- Convert DM_MMC and DM_SCSI - A20, R40, H6 Linux dts(i) sync - CLK, RESET support for sunxi, sun8_emac net drivers
2019-04-17Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx/FPGA changes for v2019.07 fpga: - Add support for external data in FIT - Extend testing for external data case - Inform user about a need to run post config on Zynq arm: - Tune zynq command functions - Fix internal variable setting arm64: - Add support for zc39dr decoding - Disable WDT for zcu100 - Small changes in reset_reason() - Some DT changes (spi) - Tune qspi-mini configuration - Remove useless eeprom setting - Fix two sdhci boot case spi: - Fix tap delay programming clk: - Enable i2c in SPL net: - Fix gem phydev handling - Remove phy detection code from gem driver general: - Correct EXT_DTB usage for MULTI_DTB_FIT configuration
2019-04-17spi: ti_qspi: Convert to spi-mem opsVignesh Raghavendra
Convert driver to use spi-mem ops in order to support accelerated MMIO flash interface in generic way and for better performance. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17spi: ti_qspi: Drop non DM codeVignesh Raghavendra
Now that all boards using TI QSPI have moved to DM and DT, drop non DM code completely. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [jagan: update MIGRATION.txt, rebase config_whitelist.txt] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17sunxi: update SATA driver to always use DM_SCSIAndre Przywara
It seems like the Allwinner SATA driver is already quite capable of using the driver model, so we can force this on all boards and can remove support for a non-DM_SCSI build. This removes the warning about boards with SATA ports not being DM_SCSI compliant. It also takes the opportunity to move the driver out of the board/sunxi directory to join its siblings in drivers/ata, and to make it a proper Kconfig citizen. The board defconfigs stay untouched. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: select DM_SCSI separately] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16net: sun8i_emac: Add CLK and RESET supportJagan Teki
Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-16net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandleJagan Teki
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16net: sunxi_emac: Add CLK supportJagan Teki
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki
GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c9698f109c1f001f80d282138a5c67cabef) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16net: gem: Remove phy autodetection codeMichal Simek
There is no reason to detect phy when core is doing it for us. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu
The phydev supported features were reset in phy_set_supported() so, move the setting of driver supported features after this so that it wont lost in phy_set_supported(). Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm: zynq: Add an info message about post configSiva Durga Prasad Paladugu
Post configuration cant be run at u-boot as u-boot didn't has any info about the design.So,this patch adds an info message that post config was not run and needs to be run manually if needed. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16ARM: zynq: Add missing i2c get_rate for fixing i2c SPLHannes Schmelzer
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C support because requesting the clock for the I2C ip-block isn't supported during SPL. To fixup this we add support requesting clocks for: - i2c0 - i2c1 Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16spi: zynqmp_gqspi: Fix tap delay values at 100MHz and 150MHzSiva Durga Prasad Paladugu
This patch fixes the tap delay values to be set at 100MHz and 150MHz as per TRM by fixing the if condition to use <= instead of <. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-12-27 06:27:38 +0000