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2019-10-13video: add support of MIPI DSI interfaceYannick Fertré
Mipi_display.c contains a set of dsi helpers. This file is a copy of file drm_mipi_dsi.c (linux kernel). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13video: stm32: stm32_ltdc: add bridge to display controllerYannick Fertré
Manage a bridge insert between the display controller & a panel. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-12Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Remember the device being emulated for Sandbox PCI - Update Kconfig options for FSP 1.0 - Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
2019-10-12Merge branch '2019-10-11-master-imports'Tom Rini
- Assorted cleanups - FAT bugfixes - mediatek platform updates
2019-10-11clk: cdce9xx: add support for cdce9xx clock synthesizerTero Kristo
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11mmc: am654_sdhci: Drop a redundant power_domain_on in probeLokesh Vutla
Power-domain is enabled by default in device_probe. am654 mmc driver is enabling power-domain again in probe. As the second call is redundant, drop power_domain_on from probe. Tested-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-11regulator: fixed: Modify enable-active-high behaviorPatrice Chotard
Regulator should not be enabled at probe time if regulator-boot-on property is not in the dt node. "enable-active-high" property is only used to indicate the GPIO polarity. See kernel documentation : - Documentation/devicetree/bindings/regulator/fixed-regulator.yaml - Documentation/devicetree/bindings/regulator/gpio-regulator.yaml Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-10-11ata: ahci: Don't forget to clear upper address regs.Oleksandr Rybalko
In 32bits mode upper bits need to be set to 0, otherwise controller will try to DMA into not existing memory and stops with error. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
2019-10-11ahci-pci: ASM1061 report wrong class, but support AHCI.Oleksandr Rybalko
Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
2019-10-11phy: mediatek: add MediaTek T-PHY support for PCIeRyder Lee
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11pci: mediatek: add PCIe controller support for MT7623Ryder Lee
This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11spi: bcm63xx_hsspi: Continue init when using no reset and fixed-clock.Kursad Oney
The Broadcom ARM implementations do not yet have a clock framework so one can use a fixed clock as the root clock of the hsspi block. The fixed clock does not have an "enable" routine, since it's always enabled. So when we hit this issue, getting an ENOSYS return, do not bail but continue initialization. Similarly the block might already have been out of reset, say, when we are booting from a SPI device. So if the reset signal is not configured in the device tree, do not bail out and instead skip deasserting the reset. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11spi: bcm63xx_hsspi: switch to raw I/O functions.Kursad Oney
Make the driver compatible with both big and little endian SOCs. Replace big-endian calls with their raw equivalents, expect for writing the command to FIFO. That still has to be in big-endian format. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-11spi: hsspi: allow to be used on bcm6858 and bcm63158Kursad Oney
This IP exists in both MIPS and ARM cores, so we also allow to use this driver on bcm6858 and bcm63158. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-11remoteproc: Introduce K3 C66 and C71 remoteproc driverLokesh Vutla
Certain SoCs with K3 architecture have integrated a C66 Corepac DSP subsystem and an advanced C71 DSPs. Introduce a remoteproc driver that that does take care of loading an elf to any of the specified DSPs and start it. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2019-10-11remoteproc: Introduce K3 remoteproc driver for R5F subsystemLokesh Vutla
SoCs with K3 architecture have an integrated Arm Cortex-R5F subsystem that is comprised of dual-core Arm Cortex-R5F processor cores. This R5 subsytem can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB. Add a remoteproc driver to support this subsystem to be able to load and boot the R5 cores primarily in LockStep mode or split mode. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2019-10-11remoteproc: tisci_proc: Add helper api for controlling core power domainLokesh Vutla
Power domain for the remote cores needs to be handled in a right sequence as mandated by the spec. Introduce tisci helper apis that can control power-domains of remote cores. TISCI clients can use this api and control the remote cores power domain instead of hooking it to power-domain layer. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11remoteproc: elf_loader: Introduce rproc_elf_get_boot_addr() apiLokesh Vutla
Introduce rproc_elf_get_boot_addr() that returns the entry point of the elf file. This api auto detects the 64/32 bit elf file and returns the boot addr accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11remoteproc: elf_loader: Introduce a common elf loader and checker functionsLokesh Vutla
Introduce a common remoteproc elf loader and checker functions that automatically detects the 64 bit elf file or 32 bit elf file and loads/checks the sections accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11remoteproc: elf-loader: Add 64 bit elf loading supportLokesh Vutla
The current rproc-elf-loader supports loading of only 32 bit elf files. Introduce support for loading of 64 bit elf files in rproc-elf-loader. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11remoteproc: elf_loader: Always check the validity of the image before loadingLokesh Vutla
rproc_elf32_load_image() rely on user to send a valid address for elf loading. Instead do a sanity check on the address passed by user. This will help all rproc elf users to not call sanity_check explicitly before calling elf_loading. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11remoteproc: ops: Add elf section size as input parameter to device_to_virt apiLokesh Vutla
Introduce a new parameter "size" that accepts size of the region to remoteproc ops callback device_to_virt(). This can enforce more checks on the region that device_to_virt() is dealing with. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11dm: core: Add a function to count the children of a deviceLokesh Vutla
Add a function to count the available children of a device. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11sandbox: pci: Remember the device being emulatedSimon Glass
Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-10mmc: stm32_sdmmc2: implement host_power_cycle callbackYann Gautier
For the correct power cycle sequence with stm32_sdmmc2, the write of the power cycle value in PWRCTL field of SDMMC_POWER register is now done in stm32_sdmmc2_host_power_cycle() and no more in stm32_sdmmc2_pwrcycle(). Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-10mmc: add a driver callback for power-cycleYann Gautier
Some MMC peripherals require specific power cycle sequence, where some registers need to be written between the regulator is turned off and then back on. This is the case for the MMC IP embedded in STM32MP1 SoC. In STM32MP157 reference manual [1], the power cycle sequence is: 1. Reset the SDMMC with the RCC.SDMMCxRST register bit. This will reset the SDMMC to the reset state and the CPSM and DPSM to the Idle state. 2. Disable the Vcc power to the card. 3. Set the SDMMC in power-cycle state. This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being supplied through the signal lines. 4. After minimum 1ms enable the Vcc power to the card. 5. After the power ramp period set the SDMMC to the power-off state for minimum 1ms. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are set to drive “1”. 6. After the 1ms delay set the SDMMC to power-on state in which the SDMMC_CK clock will be enabled. 7. After 74 SDMMC_CK cycles the first command can be sent to the card. The step 3. cannot be handled by the current framework implementation. A new callback (host_power_cycle) is created, and called in mmc_power_cycle(), after mmc_power_off(). The incorrect power cycle sequence has shown some boot failures on STM32MP1 with some SD-cards, especially on cold boots when the input frequency is low (<= 25MHz). Those failures are no more seen with this correct power cycle sequence. [1] https://www.st.com/resource/en/reference_manual/DM00327659.pdf Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-10drivers: mmc: Add sdhci driver for Broadcom iProc platformArun Parameswaran
Add SDHCI driver for iProc family of Broadcom devices. Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com> Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: Pavithra Ravi <pavithra.ravi@broadcom.com> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
2019-10-10spl: dm_mmc: Initialize only the required mmc deviceLokesh Vutla
In SPL, all the available mmc devices gets initialized during boot. This might not work in cases where clocks are not available for certain mmc devices(other than boot device) and the support for enabling device might not be ready. Texas Instruments' K3 J721E device having a central system controller (dmsc) is one such example falling in this category. Below is the sequence for the failing scenario: - ROM comes up in SD mode and loads SPL by just initialing SD card. - SPL loads dmsc firmware from SD Card. Since ROM has enabled SD, SPL need not enable the SD, just need to re initialize the card. But SPL is trying to initialize other MMC instances which are in disabled state. Since dmsc firmware is not yet available, devices cannot be enabled. So in SPL, initialize only the mmc device that is needed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-09Merge tag 'u-boot-imx-20191009' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191009 ------------------- Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532 - MX6UL / ULZ - Toradex board - Allow to set OCRAM for MX6Q/D - MX7ULP - MX8: (container image, imx8mq_mek), SCU API - fix several board booting from SD/EMMC (cubox-i for example) - pico boards [trini: display5 merged manually] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Move WATCHDOG_TIMEOUT_MSECS to Kconfig (Heiko)
2019-10-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Rename existing FSP code to fsp1 - Add fsp2 directory in preparation to support FSP 2.0 - Various x86 platform codes update - Various bug fixes and updates in dm core, sandbox and spl
2019-10-08Merge tag 'u-boot-atmel-2020.01-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features and fixes for 2020.01 cycle The feature set includes support for two new boards from Microchip AT91: The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2 SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor, QSPI, etc The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio, Camera sensor connector, etc. The full support for sam9x60ek will come at a later time. There are still missing bits regarding the clock support and power management controller.
2019-10-08Merge tag 'efi-2020-01-rc1' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc1 The major corrections in this pull request are: Fixes for the SetVariable() boot service. Device path node for NVMe drives. Disable CONFIG_CMD_NVEDIT by default.
2019-10-08pinctrl: nxp: DM_FLAG_PRE_RELOC by defaultIgor Opaniuk
For NXP SoCs we have to set pinmux configuration ASAP (ideally before relocation) to get serial console working. Without this we miss almost the half of output (U-boot version, CPU defails, Reset cause, DRAM details etc.). To achieve this we need to force appropriate pinctrl drivers to get probed before relocation. Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-08ddr: imx8m: Fix the ddr init hang on imx8mqJacky Bai
On, i.MX8MQ, the PLL config must be done when ddrmix isolation is released. So move the dram pll init after iso config done. For other i.MX8M SOC, either init pll before or after isolation is ok. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08driver: ddr: Refine the ddr init driver on imx8mJacky Bai
Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8mq: Update the ddrc QoS setting for B1 chipBai Ping
Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>
2019-10-08ddr: imx8m: Fix ddr4 driver build issueYe Li
Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08spi: fsl_qspi: Add support for QSPI on iMX7ULPYe Li
Add the compatible string and driver data for iMX7ULP platform Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08spi: fsl_qspi: Update to use driver dataYe Li
Add the driver data for each compatible string. So we can remove the SOC config and use driver data instead. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08spi: fsl_qspi: Update write data size for page program LUTYe Li
The write data size can be overwritten by writing to the IDATSZ field of IPCR register. Since the driver always updates the IDATSZ in page program operation. Set the LUT data size to 0 to align the codes with iMX. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08spi: fsl_qspi: Fix DDR mode setting for latest iMX platformsYe Li
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08misc: imx8: add more scfw apiPeng Fan
Add more scfw api for clk/partition/seco usage The api will be used by ccf/partition/secure boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08ddr: imx8m: fix ddr firmware location when enable SPL OFPeng Fan
With CONFIG_SPL_OF_CONTROL, the device tree will be padded to end of the u-boot-spl-nodtb.bin, however we also put the ddr firmware file to this location, so need to adapt the code with SPL OF and align to 4 bytes to ease copy firmware. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add support for i.MX7/i.MX8MQ reset controllerPatrick Wildt
Add support for the reset controller that's used on the i.MX7D and i.MX8MQ. This will be needed to be able to assert the PCIe reset pins. Bindings taken from Linux, driver implementation mostly taken from Linux and adjusted to U-Boot infrastructure. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-08imx: add support for i.MX8MQ power domain controllerPatrick Wildt
Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08spi: Add support for SPL_OF_PLATDATA to mxs_gpio.c driverLukasz Majewski
After this patch the mxs_gpio.c DM/DTS driver can be used at early SPL to read states of gpio pins (and for example alter the boot flow). It was necessary to adjust its name to 'fsl_imx_2{38}_gpio' to match requirements for SPL_OF_PLATDATA usage. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-08mmc: Replace printf with debug call for timeouts in the i.MX28 mxs driverLukasz Majewski
This change replaces printf() with debug() for the notification about commands timeouts. This is done on purpose (also other drivers use such approach - dw_mmc.c, mvebu_mmc.c), as the mmc core code (mmc.c) uses timeouts to assess if one is using sd card or eMMC device. In such situation timeout is a some kind of a "normal" behavior and there shall not be any output to the console. There is no impact on boot time for boards using this driver (even in SPL) when two extra timeouts are returned (no SD card present, only eMMC available). Boot time tested with grabserial: sudo grabserial -b 115200 -d /dev/ttyUSB1 -e 30 -t -m "^U-Boot SPL*" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-08mmc: Convert mxsmmc eMMC driver for i.MX2{38} to DM/DTSLukasz Majewski
This patch converts the mxsmmc driver to support DM/DTS. Moreover, it is also possible to use it in early SPL with SPL_OF_PLATDATA enabled. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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