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Pull the vidconsole_put_string() function from DM tests, make it
available to e.g. boards that want to display information on the
LCD on boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
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The IPUv3 can handle 1920x1080x32bpp displays , set the max preallocated
framebuffer BPP to 32 to cater for all eventualities.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
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This code also works with imx53 ipus so we can enable it for them.
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
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This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
causes the imx53 HSC to hang as the eMMC is not working properly anymore.
The exact error message:
MMC write: dev # 0, block # 2, count 927 ... mmc write failed
0 blocks written: ERROR
imx53 is not using the DDR mode.
Debugging of pre_div and div generation showed that those values are
generated in a way, which is not matching the ones from working setup.
As the original patch was performing code refactoring, let's revert this
change, so all imx53 boards would work again.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
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- Allow coreboot to process unhandled tags
- Enable NVMe on QEMU x86_64 target
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When dma_addr_t is u32 in 64-bit, there are some warnings when
building NVME driver. Fix it by doing an additional (long) cast.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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Also get rid of ahci_setup_port(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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The function bcm6345_wdt_start use the argument timeout
as tick but it should be used as milliseconds.
A clock is added as requirement for this driver.
The frequency of the clock is then used to convert the
millisecond to ticks in the function bcm6345_wdt_start.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
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These options only apply when not using DM_I2C. When using device
trees, the dt will enable and control the speeds of the I2C
controller(s) and these configuration options have no effect.
So disable them in DM_I2C mode. Otherwise they show up as decoys, and
make it look like one is enabling I2C controllers and setting the speed
when really it's doing nothing.
However, a system using a SPL build will not use DM_I2C in the SPL, even
if DM_I2C is enabled for the main u-boot. And so the SPL might use the
kconfig based I2C speed controls while the main u-boot does not.
Cc: Sriram Dash <sriram.dash@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
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This is an old driver that supports both device mapped and non-mapped
mode, and covers a wide range of hardware. It's hard to change without
risking breaking something. I have to tried to be exceedingly detailed
in this patch, so please excuse the length of the commit essay that
follows.
In device mapped mode the I2C xfer function does not handle plain read,
and some other, transfers correctly.
What it can't handle are transactions that:
Start with a read, or,
Have a write followed by a read, or,
Have more than one read in a row.
The common I2C/SMBUS read register and write register transactions
always start with a write, followed by a write or a read, and then end.
These work, so the bug is not apparent for most I2C slaves that only use
these common xfer forms.
The existing xfer loop initializes by sending the chip address in write
mode after it deals with bus arbitration and master setup. When
processing each message, if the next message will be a read, it sends a
repeated start followed by the chip address in read mode after the
current message.
Obviously, this does not work if the first message is a read, as the
chip is always addressed in write mode initially by i2c_init_transfer().
A write following a read does not work because the repeated start is
only sent when the next message is a read. There is no logic to send it
when the current message is a read and next is write. It should be sent
every time the bus changes direction.
The ability to use a plain read was added to this driver in
commit 2feec4eafd40 ("imx: mxc_i2c: tweak the i2c transfer method"),
but this applied only the non-DM code path.
This patch fixes the DM code path. The xfer function will call
i2c_init_transfer() with an alen of -1 to avoid sending the chip
address. The same way the non-DM code achieves this. The xfer
function's message loop will send the address and mode before each
message if the bus changes direction, and on the first message.
When reading data, the master hardware is one byte ahead of what we
receive. I.e., reading a byte from the data register returns a byte
*already received* by the master, and causes the master to start the RX
of the *next* byte. Therefor, before we read the final byte of a
message, we must tell the master what to do next. I add a "last" flag
to i2c_read_data() to tell it if the message is to be followed by a stop
or a repeated start. When last == true it acts exactly as before.
The non-DM code can only create an xfer where the read, if any, is the
final message of the xfer. And so the only callsite of i2c_read_data()
in the non-DM code has the "last" parameter as true. Therefore, this
change has no effect on the non-DM code. As all other changes are in
the DM xfer function, which is not even compiled in non-DM code, I am
confident that this patch has no effect on boards not using I2C_DM.
This greatly reduces the range of hardware that could be affected.
For DM boards, I have verified every transaction the "i2c" command can
create on a scope and they are all exactly as they are supposed to be.
I also tested write->read->write, which isn't possible with the i2c
command, and it works as well. I didn't fix multiple reads in a row, as
it's a lot more invasive and obviously no one has every wanted them
since they've never worked. It didn't seem like the extra complexity
was justified to support something no one uses.
Cc: Nandor Han <nandor.han@ge.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Breno Matheus Lima <brenomatheus@gmail.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
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It is not very clear how these work in relation to the exact I2C xfers
they produce. In paticular, the address length is somewhat overloaded
in the read method. Clearly document the existing behavior. Maybe this
will help the next person who needs to work on this driver and not break
non-DM boards.
Cc: Nandor Han <nandor.han@ge.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Breno Matheus Lima <brenomatheus@gmail.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
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- micrel, ti PHY fixes
- rtl8169, mtk-eth fixes
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STM32 MCUs update:
_ Add MPU region for SPI NOR memory mapped region
_ Add missing QSPI flash compatible for STM32 F7 boards
_ Update spi-tx-bus-width and spi-rx-bus-width properties
_ Add QSPI support for STM32F469 Discovery board
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In mt7629-rfb.dts, the phy-handle is a reference to the node phy0, not the
node itself:
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
}
However the driver used ofnode_find_subnode("phy-handle") to read the node.
It will always fail.
This patch replaces ofnode_find_subnode with dev_read_phandle_with_args to
make sure the node can be read correctly.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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This version of the RTL-8168 is present on some development boards and
is compatible with this driver. Add support for identifying this version
of the chip so that U-Boot won't complain about it being unknown.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Implement this callback that allows the MAC address to be set for the
Ethernet card. This is necessary in order for the device to be able to
receive packets for the MAC address that U-Boot advertises.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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There is a need to fill node before clk_output_sel is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Reviewed-by: <hannes.schmelzer@br-automation.com>
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Commit d397f7c45b0b ("net: phy: micrel: Separate KSZ9000 drivers from
KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
that you shouldn't select both of them due to a device ID clash between
the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
the Linux Micrel PHY driver provides a solution by using different PHY
ID and mask values to distinguish these chips.
This commit contains the following changes:
- The PHY ID and mask values for the KSZ9021 and the KS8721 now match
those used by the Linux driver.
- The warnings about not enabling both drivers have been removed.
- The description for PHY_MICREL_KSZ8XXX has been corrected (these are
10/100 PHYs, not GbE PHYs).
- PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
since this is selected by PHY_MICREL_KSZ90X1.
- All of the relevant defconfig files have been updated now that
PHY_MICREL_KSZ8XXX does not default to 'Y'.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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- A10 FPGA programming support, Gen5 livetree conversion
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Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Convert 'socfpga_reset_probe' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int'.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to
read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to
read flash (child node) parameters.
Tested on socfpga_socrates (socfpga gen5).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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The dw-apb timer does not use 'gd', so remove its declaration.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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Drop unused macros from the header to clean it up.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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There is no RTS7751R2D support in U-Boot, drop all the RTS7751R2D macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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There is no SH2007 support in U-Boot, drop all the SH2007 macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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There is no H8 support in U-Boot, drop all the H8 macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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There is no 'config CRC32' remove the select that was attempting to use
it.
Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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CONFIG_GPIO does not exist. sysreset_gpio.c uses the DM gpio APIs so the
correct option to select is DM_GPIO.
Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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There is one case where 400ms is not sufficient for loading the
system firmware:
- System firmware is not signed with rsa degenerate key.
- ROM loading the sysfw directly from SPI flash which is in memory
mapped mode.
The above scenario is definitely not desired in production use cases
as it effects boot time. But still keeping this support as this is
a valid boot scenario.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Fix test_avb_persistent_values() pytest, which was failing because of
wrong size value provided from tee sandbox driver.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
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malloc(..) and memalign(..) are both allocating memory and as a result
we leak the memory allocated with malloc(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Per feedback from Marek, he suggested better handling and
to enable DM_FLAG_OS_PREPARE, this patch re-orders some of
the error checking, and errors returns the error code right
away and also sets DM_FLAG_OS_PREPARE.
Signed-off-by: Adam Ford <aford173@gmail.com>
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Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
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- Add USB PHY drivers for Amlogic G12A
- Add USB Complex Glue driver for Amlogic G12A
- Add USB Gadget support for Amlogic G12A
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This adds support for the USB PHYs found in the Amlogic G12A SoC Family.
The USB2 PHY supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.
The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on
the layout of the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Adds support for Amlogic G12A USB Control Glue HW.
The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only
A glue connects these both controllers to 2 USB2 PHYs, and optionnally
to an USB3+PCIE Combo PHY shared with the PCIE controller.
The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including
routing of the OTG PHY between the DWC3 and DWC2 controllers, and
setups the on-chip OTG mode selection for this PHY.
This driver sets the OTG capable port as Host mode by default,
the switch to Device mode is to be done in a separate patch.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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- Various PHY fixes / enhancements.
- TI K2G fixes
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In some of the device trees that specify skew values for KSZ90x1 PHYs
the values are stored (incorrectly) in the MAC node, whereas in others
it is in an 'ethernet-phy' subnode. Previously the code would fail to
find and program these skew values, so this commit changes it to look
for an "ethernet-phy" subnode first, and revert to looking in the MAC
node if there isn't one.
The device trees affected (where the skew values are in a subnode) are
imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts,
r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi,
sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts,
socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew
values in these device trees would be ignored.
The device trees where the skew values are in the MAC node are
socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts,
socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts,
socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts,
socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be
unaffected by this change.
The changes were tested on a sama5d3xcm.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.
The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).
This commit sorts out the resulting confusion in a consistent way by
making the following changes:
- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.
- Update the Micrel PHY driver to select the appropriate divisor for
both parts.
- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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For AQR405 in register 4.c441 bit 15 was override with 0. This caused the
phy to not negotiate at 2.5GB rate with mac. To avoid
this override it needed first to know the previous value of reg 4.c441
and set only bit 3.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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