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2018-07-19drivers: smem: sandboxRamon Fried
Add Sandbox driver for SMEM. mostly stub operations. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19soc: qualcomm: Add Shared Memory Manager driverRamon Fried
The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Adapted from the Linux driver (4.17) Changes from the original Linux driver: * Removed HW spinlock mechanism, which is irrelevant in U-boot particualar use case, which is just reading from the smem. * Adapted from Linux driver model to U-Boot's. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19dm: SMEM (Shared memory) uclassRamon Fried
This is a uclass for Shared memory manager drivers. A Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-19ARM: qemu-arm: enable RTCHeinrich Schuchardt
QEMU provides an emulated ARM AMBA PrimeCell PL031 RTC. The patch sets the base address in the board include file according to the definition in hw/arm/virt.c of the QEMU source. It defines the Kconfig option for the existing driver, and enables the RTC driver in qemu_arm64_defconfig and qemu_arm_defconfig as well as the date command. We need an RTC to provide the GetTime() runtime service in the UEFI subsystem. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Tested-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2018-07-19power: regulator: stpmu1: add power off delayChristophe Kerello
This patch adds a delay when regulators are disabled. This delay is set to 5 ms to cover all use cases. The worst use case actually seen is during a SD card power cycle. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19phy: Be able to get phy from PHY providerPatrice Chotard
In case of phy are provided from a PHY provider nodes as following: usbphyc: usb-phy@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc_clk USBPHY_K>; resets = <&rcc_rst USBPHY_R>; #address-cells = <1>; #size-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <1>; }; }; and PHY are called as following: usbh_ehci: usbh-ehci@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc_clk USBH>; resets = <&rcc_rst USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>; companion = <&usbh_ohci>; phys = <&usbphyc_port0>; phy-names = "usb"; status = "okay"; }; generic_phy_get_by_index() must be updated to first look for PHY phandle as previously and in case of error looks for PHY provider by finding the parent's current node which is the PHY provider. args (ofnode_phandle_args struct) must also be updated by inserting the phy index into the PHY provider as args[0]. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19mmc: stm32_sdmmc2: update pwron managementPatrick Delaunay
Correctly manage the SDMMC reset and card cycle power to fully handle the power cycle added in the MMC uclass and avoid issue with level-shifter with some uSDCARD. 3 states managed in driver: 1/ reset: SDMMC disable, signal HiZ 2/ power-cycle: SDMMC disable, signals drive to 0 3/ power-on: SDMMC enabled Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19drivers: fpga: zynqpl: fix compilation with SPLLuis Araneda
Disable the use of function zynq_loadfs when compiling the driver for the SPL, as the following filesystem functions are not found by the linker: - fs_set_blk_dev - fs_read - fs_set_blk_dev - fs_read - fs_read Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: cadence: Do not stop wdt in probeMichal Simek
Watchdog can be started before probe and u-boot should just take control over it. That's why do not stop watchdog in probe to cover cases where watchdog can expire before probe and start. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: cdns: Add comment for expire_now functionMichal Simek
IP itself has no reg/no bit which can be used for this functionality. Add this note to the driver to make sure that none will be asking for that. Current method is to setup 1s timeout and hang() which is done via wdt_expire_now(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19microblaze: Convert generic platform to DM gpioMichal Simek
Converting GPIO to DM requires to do changes in reset subsystem that's why support for Microblaze soft reset via sysreset and GPIO sysreset support was added. These two patches enables enabling GPIO DM. Microblaze soft reset is bind at last reset method. GPIO reset is handled via sysreset with adding this fragment to DT. gpio-restart { compatible = "gpio-restart"; gpios = <&reset_gpio 0 0 0>; /* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */ }; hard-reset-gpio property is not documented and also handled. Conversion is required. Unfortunately do_reset is required for SPL that's why use only soft microblaze reset for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: Convert Xilinx Axi watchdog driver to driver modelShreenidhi Shedi
Xilinx Axi wdt driver conversion to driver model & Kconfig update for the same. Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19gpio: xilinx: Convert driver to DMMichal Simek
This patch is enabling GPIO_DM support to have an option to use this driver together with zynq gpio driver. !DM part is kept there till Microblaze is cleanup which will be done hopefully soon. Just a note: There is no reason to initialize uc-priv->name because it is completely unused. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19sysreset: Add support for Microblaze soft reset jumpMichal Simek
Microblaze is storing reset vector at address 0x0. It means soft reset can be done by just jumping to this address. This code was in platform code but sysreset interface is providing enough capabilities to have more options how to reset the system. It can go from gpio reset through watchdog reset till soft reset. The driver has not compatible string because this is cpu specific and DM core is not able to detect compatible string in DT root that's why this driver will be instantiated from platform code by calling device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft", NULL); It should be bind as the last reset method to ensure that hw reset is called before this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19sysreset: Add support for gpio-restartMichal Simek
The Linux kernel has binding for gpio-restart node. This patch is adding basic support without supporting any optional properties. This driver was tested on Microblaze system where gpio is connected to SoC reset logic. Output value is handled via gpios cells values. In gpio_reboot_request() set_value is writing 1 because dm_gpio_set_value() is capable to changing it when it is ACTIVE_LOW. ... if (desc->flags & GPIOD_ACTIVE_LOW) value = !value; ... Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Setup bank_name to dev->nameMichal Simek
There should be proper bank name setup to distinguish between different gpio drivers. Use dev->name for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Read of mach data in platdata with dev_get_driver_dataMichal Simek
Remove bogus zynq_gpio_getplat_data() and read driver data directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: dm: Support manual relocation for gpioMichal Simek
Relocate gpio ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19sysreset: dm: Support manual relocation for sysresetMichal Simek
Relocate sysreset ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Fix typo in one error messageMichal Simek
Just fix error message. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: dm: Support manual relocation for watchdogsMichal Simek
Relocate watchdog ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19watchdog: dm: Change uclass name to watchdog and enable DM_UC_FLAG_SEQ_ALIASMichal Simek
uclass name is used by dev_read_alias_seq which return seq number when aliases are used. Code fragment: 168 int dev_read_alias_seq(struct udevice *dev, int *devnump) 169 { 170 ofnode node = dev_ofnode(dev); 171 const char *uc_name = dev->uclass->uc_drv->name; 172 int ret; 173 174 if (ofnode_is_np(node)) { 175 ret = of_alias_get_id(ofnode_to_np(node), uc_name); Also this patch enables DM_UC_FLAG_SEQ_ALIAS to be in sync with Linux which is also using watchdog name for watchdog aliases. drivers/watchdog/watchdog_core.c:215: ret = of_alias_get_id(wdd->parent->of_node, "watchdog"); Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19serial: zynq: Use platdata for storing static data instead of privMichal Simek
Explanation from Simon Glass "Private data is created when the device is probed and freed when the device is removed. Platform data is created when the device is bound, and survives probe/remove cycles. Strictly speaking, platform data should be used to hold the decoded device tree properties. Private data should be used for run-time things the device needs to keep track of." Based on description the driver needs to be switch to use platdata instead of priv. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19clk: zynqmp: Fixed the same if/else part error reported by coverityVipul Kumar
This patch fixed the same if/else part error by adding the required source select on the basis of is_pre_src check. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19gpio: zynq: Use live-tree functionMichal Simek
Use live-tree function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-07-16sf: add paired dev info for winbond w25q16jvLudwig Zenz
This commit adds paired dev info for winbond w25q16jv (tested w25q16jvssiq with a i.mx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Macronix mx25l1633e entryLudwig Zenz
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Gigadevice gd25q16c entryLudwig Zenz
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi_flash: add a bunch of winbond flashes to id-tableHannes Schmelzer
This commit adds the following flashes to the id-table - W25Q16JV - W25Q32JV - W25Q64JV - W25Q128JV - W25Q256JV Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: zynqmp_gqspi: Add support for ZynqMP qspi driverSiva Durga Prasad Paladugu
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> [jagan: removed GQSPI_MIO_NUM_ macros] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: convert to livetreeVipul Kumar
Update the xilinx spi driver to support a live tree. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Added support to read JEDEC-id twice at the boot timeVipul Kumar
This patch is for the startup block issue in the spi controller. SPI clock is passing through STARTUP block to FLASH. STARTUP block don't provide clock as soon as QSPI provides command. So, first command fails. This patch added support to read JEDEC id in xilinx_spi_xfer (). Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() functionVipul Kumar
This patch modify xilinx_spi_xfer() function and add rxfifo() and txfifo() functions to add the modularity so that these functions can be used by other functions within the same file. This patch also added support to read fifo_size from dts. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx: Read reg base address from DTS fileMichal Simek
This patch added support to read register base address from DTS file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: support R40 GMACLothar Felten
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: set mux and clock by driver dataLothar Felten
Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16net: sun8i-emac: fix printing NULL characterLothar Felten
If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16dm: mmc: sunxi: Add A10/A20 compatible stringsAdam Sampson
Commit dd27918c2252 ("dm: mmc: sunxi: Add support for driver model") only added the allwinner,sun5i-a13-mmc compatible string for this driver. The DM initialisation code here also works with (at least) A10 and A20, so add the appropriate compatible strings as per Linux 4.17's driver. Tested on A10 Cubieboard and A20 pcDuino3 Nano with CONFIG_DM_MMC. (A20 worked already, because sun7i-a20.dtsi specifies both the A13 and A20 strings.) Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2018-07-13Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-12lpi2c: Add bus busy error handlingYe Li
When doing "i2c dev 4; i2c probe" with ENET daughter card connected on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of lpi2c always show busy, but the master is idle, and stop is detected (SDF set). This patch addes a handling to re-init the lpi2c master for this case. Then the issue can be worked around. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12lpi2c: Fix bus stop problem in xferYe Li
In xfer function, both bus_i2c_read and bus_i2c_write will send a STOP command. This causes a problem when reading register data from i2c device. Generally two operations comprise the register data reading: 1. Write the register address to i2c device. START | chip_addr | W | ACK | register_addr | ACK | 2. Read the Data from i2c device. START | chip_addr | R | ACK | DATA | NACK | STOP The STOP command should happen at the end of the transfer, otherwise we will always get data from register address 0 Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12imx: lpi2c: fix clock issue when NACK detectedGao Pan
For LPI2C IP, NACK is detected by the rising edge of the ninth clock. In current uboot driver, once NACK is detected, it will reset and then disable LPI2C master. As a result, we can never see the falling edge of the ninth clock. Signed-off-by: Gao Pan <pandy.gao@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12imx_lpi2c: Update lpi2c driver to support imx8Ye Li
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory to u-boot include directory as a common header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut
The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut
This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12spi: cadence_qspi: Fix warning cast from pointer to integer of different sizeLey Foon Tan
Use "%p" to print cmdbuf. Compilation warning as below: CC spl/drivers/spi/cadence_qspi_apb.o LD spl/lib/built-in.o drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’: drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] cmdlen, (unsigned int)cmdbuf); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12spi: cadence_qspi: Fix compilation warningLey Foon Tan
Use "%zu" for size_t data type. Compilation warning as below: In file included from include/linux/bug.h:7:0, from include/common.h:26, from drivers/spi/cadence_qspi.c:8: drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’: drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=] debug("%s: len=%d [bytes]\n", __func__, data_bytes); ^ include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’ #define pr_fmt(fmt) fmt ^~~ include/log.h:142:2: note: in expansion of macro ‘debug_cond’ debug_cond(_DEBUG, fmt, ##args) ^~~~~~~~~~ drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’ debug("%s: len=%d [bytes]\n", __func__, data_bytes); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>