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2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDR4 mr detectionJagan Teki
Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held. Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization. So, add code to support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Handle data training via opsJagan Teki
data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Simplify data training first argumentJagan Teki
data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition. This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref_mode_acJagan Teki
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8% Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 mode_sel based on io settingsJagan Teki
The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref based on io settingsJagan Teki
The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Get lpddr4 tsel_rd_en from io settingsJagan Teki
For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure soc odt supportJagan Teki
CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399. These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Add tsel control clock driveJagan Teki
tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: sdram: Configure lpddr4 tsel rd, wr based on IO settingsJagan Teki
Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Add IO settingsJagan Teki
Add IO settings for dram ctl and phy. IO settings are useful for configuring ctl, phy odt, vref, mr5, mode select and other needed input output operations for lpddr4 or any other dramtype sdram. Right now, this patch added IO setting for all supported sdram frequencies. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1Jagan Teki
The hardware for LPDDR4 with - CLK0P/N connect to lower 16-bits - CLK1P/N connect to higher 16-bits and usually dfi dram clk is configured via CLK1P/N, so disabling dfi dram clk will disable the CLK1P/N as well. So, add patch to not to disable dfi dram clk for lpddr4, with rank 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure tsel write ca for lpddr4Jagan Teki
tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt. Configure the same PHY register for lpddr4 would require a mask value of (300 << 8). Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Map chipselect for lpddr4Jagan Teki
Assign desired cs_map values for lpddr4 during set memory map. Initial cs_map values is based on the sdram parameters, so the same will adjusted based dramtype as LPDDR4. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4Jagan Teki
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4Jagan Teki
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4Jagan Teki
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure PHY_898, PHY_919 for lpddr4Jagan Teki
PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4. So, configure the same in pctl_cfg for LPDDR4. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Avoid two channel ZQ Cal Start at the same timeJagan Teki
It is possible in lpddr4 dram, where both the channels would start at same time with ZQ Cal Start. If it uses ZQ Call start then it will use RZQ. For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe connect to both channel. If ZQ Cal Start at the same time, it will use the same RZQ. It is not a problem of using RZQ in both the channels, but can not use at the same time. So, to avoid this, we have an option of dram tINIT3 value for increasing the frequency for channel 1. This patch increase the available tINIT3 with existing running dram frequency. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Don't wait for PLL lock in lpddr4Jagan Teki
lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Move mode_sel assignmentJagan Teki
mode_sel assignment is based on dram type. In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 rank mask for wdql trainingJagan Teki
Add rank_mask based on the rank number for lpddr4. This would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 rank mask for ca trainingJagan Teki
Add rank_mask based on the rank number for lpddr4. This would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rockchip: Kconfig: Add RK3399 LPDDR4 entryJagan Teki
Supporting LPDDR4 code support in RK3399 would increases the size of SPL/TPL. So add kconfig entry for RK3399 LPDDR4 code so-that the boards have LPDDR4 can enable them via defconfig. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure phy IO in ds odtJagan Teki
Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt. For those cases the set_ds_odt would be an initial call to setup the phy. To satisfy all the cases, trigger phy IO from set_ds_odt. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add DdrModeJagan Teki
Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddrtimingC0Jagan Teki
Add DdrTimingC0 structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddr version enc macroJagan Teki
Add dram config macro for handling ddr version number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Introduce sys_reg3 for more capacity infoJagan Teki
cs0_row, cs1_row and cs1_col needs more bits to show its correct value, update to make use of both sys_reg2, sys_reg3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash similar patches into one patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Rename sys_reg with sys_reg2Jagan Teki
Use dram config variable name as sys_reg2 instead of sys_reg since the final variable value is to written into a pmugrf register named as sys_reg2. This reflect the both variable and associated register names are same and also help to add next sys_reg's to add it in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Simply existing dram enc macroJagan Teki
Add simplified and meaningful macro for all setting. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash the similar patches into 1 patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Enable sdram debug functionsJagan Teki
This would help to debug the sdram base parameters while debugging existing chip or while supporting new sdram type. It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG for showing the debug prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add rank detection supportJagan Teki
Right now the rk3399 sdram driver assume that the board has configured with 2 channels, so any possibility to enable single channel on the same driver will encounter channel #1 data training failure. Log: U-Boot TPL board init sdram_init: data training failed rk3399_dmc_init DRAM init failed -5 So, add an algorithm that can capable to compute the active or configured rank with associated channel like a) do rank loop to compute the active rank, with associated channel numbers b) then, succeed the data training only for configured channel c) preserve the rank for given channel d) do channel loop for setting the active channel e) if given rank is zero or inactive on the specific channel, clear the timings for the associated channel f) finally, return error if number of channels is zero Tested in NanoPI-NEO4 since it support single channel sdram configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19serial: mxc: Add compatibles to NXP's serial driver (for imx21 and imx53)Lukasz Majewski
This patch fixes not enabled uart2 (and hence serial console) on i.MX53 devices. After following commit 1d255904c306 ("ARM: dts: imx: imx53: Synchronize iMX53 DT with Linux") from the uart2 compatible the 'fsl,imx7d-uart' has been removed (which was correct). However, the root cause of the problem was the commit 98d62e618bb9 ("arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC") which introduced this compatible. Moreover, without this patch all i.MX53 UARTs are not usable as neither 'fsl,imx53-uart' nor 'fsl,imx21-uart' are in compatible IDs in drivers/serial/serial_mxc.c file. The fix is to add 'fsl,imx53-uart' and 'fsl,imx21-uart' as compatibles for the aforementioned serial driver (those are also defined in the Linux kernel). Signed-off-by: Lukasz Majewski <lukma@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2019-07-19IMX: serial: dm: Set DM_FLAG_PRE_RELOC in the IMX uart driverLukasz Majewski
The DM_FLAG_PRE_RELOC shall be set unconditionally as this driver is going to be re-used in both early SPL and U-Boot proper's pre-reloc. For i.MX based devices it is crucial to have available the serial console before relocation (otherwise the board may hand). The device definition may be provided either via device tree description or with U_BOOT_DEVICE(mxc_serial) definition. In the latter case the device will not bind in U-Boot proper when DM_FLAG_PRE_RELOC is not set. The !CONFIG_IS_ENABLED(OF_CONTROL) #if check was set as a "workaround" for DM problem described in following commit 4687919684e0 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers"). Let's look on this check more thoroughly - we add this flag if the board doesn't support OF_CONTROL. This is a bit strange as the serial_mxc.c can be used with CONFIG_DM_SERIAL but without corresponding device tree description (OF_CONTROL). In such case the aforementioned U_BOOT_DEVICE(mxc_serial) definition is used. Other boards/SoCs have this flag set unconditionally for serial driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19watchdog: imx: Add DM supportMarek Vasut
Add DM and DT probing support to iMX watchdog driver. This should allow boards to move over to this driver, enable SYSRESET_WATCHDOG to handle cpu_reset() if required. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
2019-07-19watchdog: Split WDT from SPL_WDTMarek Vasut
Use CONFIG_IS_ENABLED(WDT) to permit use of WDT in SPL without DM, while the full U-Boot can use rich DM/DT WDT driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Suniel Mahesh <sunil.m@techveda.org>
2019-07-19gpio: Add missing parenthesis to the GPIO_TO_PORT defineLukasz Majewski
Add missing parenthesis to the GPIO_TO_PORT macro. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19pwm: imx: add DM_PWM supportHeiko Schocher
add DM support for pwm-imx driver. Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-19pwm: imx: add Kconfig supportHeiko Schocher
add Kconfig support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Martyn Welch <martyn.welch@collabora.co.uk>
2019-07-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- Update SiFive Unleashed clock driver. - Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board
2019-07-19regulator: bd718x7: support ROHM BD71837 and BD71847 PMICsMatti Vaittinen
BD71837 and BD71847 is PMIC intended for powering single-core, dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847 is used for example on NXP imx8mm EVK. Add regulator driver for ROHM BD71837 and BD71847 PMICs. BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version containing 6 bucks and 6 LDOs. Voltages for DVS bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted when regulators are enabled. For other bucks and LDOs we may have over- or undershooting if voltage is adjusted when regulator is enabled. Thus this is prevented by default. BD718x7 has a quirk which may leave power output disabled after reset if enable/disable state was controlled by SW. Thus the SW control is only allowed for BD71837 bucks 3 and 4 by default. The impact of this limitation must be evaluated board-by board and restrictions may need to be modified. (Linux driver get's these limitations from DT and we may want to implement same on u-Boot driver). Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-19thermal: add i.MX8 thermal driverPeng Fan
Add i.MX8 thermal driver to support get temperature from SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19misc: imx8: add sc_misc_get_tempPeng Fan
Add sc_misc_get_temp to support get temperature Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-19spi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)Lukasz Majewski
This patch converts mxs_spi driver to support DM/DTS. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19pinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driverLukasz Majewski
The code responsible for setting proper values in the MUX registers (in the mxs_pinctrl_set_state()) has been ported from Linux kernel - SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable. As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes, it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also make them 'visible' by the DM's "gpio_mxs" driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19gpio: mxs: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO)Lukasz Majewski
This patch adds support for DM/DTS in the mxs_gpio.c driver. Information regarding per gpio controller pin number is passed via DTS. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19net: fec: Enable support for i.MX28 DM_ETH in the fec_mxc.c driverLukasz Majewski
The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled. One only needs to add proper compatible and dependency on FEC_MXC in the Kconfig. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
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