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/*
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
/*
* Initial timer set constants. Nothing complicated, just set for a 1ms
* tick.
*/
#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
#define TIMER_COUNT (TIMER_INTERVAL / 2)
#define TIMER_PULSE TIMER_COUNT
/*
* Handy KS8695 register access functions.
*/
#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
ulong timer_ticks;
int timer_init (void)
{
/* Set the hadware timer for 1ms */
ks8695_write(KS8695_TIMER1, TIMER_COUNT);
ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
ks8695_write(KS8695_TIMER_CTRL, 0x2);
timer_ticks = 0;
return 0;
}
ulong get_timer_masked(void)
{
/* Check for timer wrap */
if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
/* Clear interrupt condition */
ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
timer_ticks++;
}
return timer_ticks;
}
ulong get_timer(ulong base)
{
return (get_timer_masked() - base);
}
void __udelay(ulong usec)
{
ulong start = get_timer_masked();
ulong end;
/* Only 1ms resolution :-( */
end = usec / 1000;
while (get_timer(start) < end)
;
}
void reset_cpu (ulong ignored)
{
ulong tc;
/* Set timer0 to watchdog, and let it timeout */
tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
ks8695_write(KS8695_TIMER_CTRL, tc);
ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
/* Should only wait here till watchdog resets */
for (;;)
;
}
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