1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
/*
* DDR Configuration for AM33xx devices.
*
* Copyright (C) 2011 Texas Instruments Incorporated -
http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/io.h>
#include <asm/emif.h>
/**
* Base address for EMIF instances
*/
static struct emif_reg_struct *emif_reg = {
(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
/**
* Base address for DDR instance
*/
static struct ddr_regs *ddr_reg[2] = {
(struct ddr_regs *)DDR_PHY_BASE_ADDR,
(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
/**
* Base address for ddr io control instances
*/
static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
/**
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs)
{
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
}
/**
* Set SDRAM timings
*/
void set_sdram_timings(const struct emif_regs *regs)
{
writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
}
/**
* Configure DDR PHY
*/
void config_ddr_phy(const struct emif_regs *regs)
{
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
}
/**
* Configure DDR CMD control registers
*/
void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
}
/**
* Configure DDR DATA registers
*/
void config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
}
void config_io_ctrl(struct ddr_ioctrl *ioctrl)
{
writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
}
|
