1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_lsch2.h>
struct serdes_config {
u32 protocol;
u8 lanes[SRDS_MAX_LANES];
};
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
{0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
{0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
{0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
SGMII_FM1_DTSEC6} },
{0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
SGMII_FM1_DTSEC6} },
{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
{0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
{0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
{0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
{0x0506, {NONE, PCIE2, NONE, PCIE3} },
{0x0559, {NONE, PCIE2, PCIE3, SATA1} },
{0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
{0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
{}
};
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == cfg)
return ptr->lanes[lane];
ptr++;
}
return 0;
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == prtcl)
break;
ptr++;
}
if (!ptr->protocol)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)
return 1;
}
return 0;
}
|
