arch/arm/dts/bitmain-antminer-s9.dts


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

// SPDX-License-Identifier: GPL-2.0
/*
 * Bitmain Antminer S9 board DTS
 *
 * Copyright (C) 2018 Michal Simek
 * Copyright (C) 2018 VanguardiaSur
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	model = "Bitmain Antminer S9 Board";
	compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart1;
		mmc0 = &sdhci0;
		gpio0 = &gpio0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		bootcount@efffff0 {
			reg = <0xefffff0 0x10>;
			no-map;
		};

		fpga_space@f000000 {
			reg = <0xf000000 0x1000000>;
			no-map;
		};
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};
};

&clkc {
	ps-clk-frequency = <33333333>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	/* 0362/5e62 */
	ethernet_phy: ethernet-phy@1 {
		reg = <1>;
	};
};

&sdhci0 {
	u-boot,dm-pre-reloc;
	status = "okay";
	disable-wp;
};

&uart1 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&watchdog0 {
	reset-on-timeout;
	timeout-sec = <200>;
};