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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1028a SOC common device tree source
*
* Copyright 2019 NXP
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1028a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
clockgen: clocking@1300000 {
compatible = "fsl,ls1028a-clockgen";
reg = <0x0 0x1300000 0x0 0xa0000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
memory@01080000 {
device_type = "memory";
reg = <0x00000000 0x01080000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06040000 0 0x40000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
};
gic_lpi_base: syscon@0x80000000 {
compatible = "gic-lpi-base";
reg = <0x0 0x80000000 0x0 0x100000>;
max-gic-redistributors = <2>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
};
fspi: flexspi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
serial1: serial@21c0600 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pcie@3400000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000
0x00 0x03480000 0x0 0x40000 /* lut registers */
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
0x80 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie@3500000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000
0x00 0x03580000 0x0 0x40000 /* lut registers */
0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
0x88 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie@1f0000000 {
compatible = "pci-host-ecam-generic";
/* ECAM bus 0, HW has more space reserved but not populated */
bus-range = <0x0 0x0>;
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
enetc0: pci@0,0 {
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
enetc1: pci@0,1 {
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
enetc2: pci@0,2 {
reg = <0x000200 0 0 0 0>;
status = "okay";
phy-mode = "internal";
};
mdio0: pci@0,3 {
#address-cells=<0>;
#size-cells=<1>;
reg = <0x000300 0 0 0 0>;
status = "disabled";
};
enetc6: pci@0,6 {
reg = <0x000600 0 0 0 0>;
status = "okay";
phy-mode = "internal";
};
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c4: i2c@2040000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c5: i2c@2050000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c6: i2c@2060000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c7: i2c@2070000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
lpuart0: serial@2260000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
interrupts = <0 232 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
lpuart1: serial@2270000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
interrupts = <0 233 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
lpuart2: serial@2280000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2280000 0x0 0x1000>;
interrupts = <0 234 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
lpuart3: serial@2290000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2290000 0x0 0x1000>;
interrupts = <0 235 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
lpuart4: serial@22a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x22a0000 0x0 0x1000>;
interrupts = <0 236 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
lpuart5: serial@22b0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x22b0000 0x0 0x1000>;
interrupts = <0 237 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
little-endian;
status = "disabled";
};
usb1: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
status = "disabled";
};
usb2: usb3@3110000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
status = "disabled";
};
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <5>;
litte-endian;
status = "disabled";
};
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <5>;
little-endian;
status = "disabled";
};
dspi2: dspi@2120000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <5>;
little-endian;
status = "disabled";
};
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
bus-width = <4>;
status = "disabled";
};
esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
non-removable;
bus-width = <4>;
status = "disabled";
};
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
reg-names = "sata-base", "ecc-addr";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt";
reg = <0x0 0xc000000 0x0 0x1000>;
};
};
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