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// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale ls1021a TWR board common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
#include "ls1021a.dtsi"
/ {
model = "LS1021A TWR Board";
aliases {
enet2-rgmii-phy = &rgmii_phy1;
enet0-sgmii-phy = &sgmii_phy2;
enet1-sgmii-phy = &sgmii_phy0;
spi0 = &qspi;
spi1 = &dspi1;
};
chosen {
stdout-path = &uart0;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: n25q128a13@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&dspi1 {
bus-num = <0>;
status = "okay";
dspiflash: at26df081a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
ranges = <0x0 0x0 0x60000000 0x08000000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
};
&lpuart0 {
status = "okay";
};
&mdio0 {
sgmii_phy0: ethernet-phy@0 {
reg = <0x0>;
};
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&sata {
status = "okay";
};
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