summaryrefslogtreecommitdiff
path: root/arch/arm/dts/r8a7795-h3ulcb.dts
blob: df50bf46406e6e904f31541e1767a1dfe8b4b25a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
 *
 * Copyright (C) 2016 Renesas Electronics Corp.
 * Copyright (C) 2016 Cogent Embedded, Inc.
 */

/dts-v1/;
#include "r8a7795.dtsi"
#include "ulcb.dtsi"

/ {
	model = "Renesas H3ULCB board based on r8a7795 ES2.0+";
	compatible = "renesas,h3ulcb", "renesas,r8a7795";

	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0x0 0x48000000 0x0 0x38000000>;
	};

	memory@500000000 {
		device_type = "memory";
		reg = <0x5 0x00000000 0x0 0x40000000>;
	};

	memory@600000000 {
		device_type = "memory";
		reg = <0x6 0x00000000 0x0 0x40000000>;
	};

	memory@700000000 {
		device_type = "memory";
		reg = <0x7 0x00000000 0x0 0x40000000>;
	};
};

&du {
	clocks = <&cpg CPG_MOD 724>,
		 <&cpg CPG_MOD 723>,
		 <&cpg CPG_MOD 722>,
		 <&cpg CPG_MOD 721>,
		 <&cpg CPG_MOD 727>,
		 <&versaclock5 1>,
		 <&versaclock5 3>,
		 <&versaclock5 4>,
		 <&versaclock5 2>;
	clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};