summaryrefslogtreecommitdiff
path: root/arch/arm/dts/rk3368-lion-u-boot.dtsi
blob: 2053fb149544a11ee3b863c47aa048db22fc85f3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
/*
 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
 *
 * SPDX-License-Identifier:     GPL-2.0+	X11
 */

/ {
	config {
		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
	};

	chosen {
		stdout-path = "serial0:115200n8";
		u-boot,spl-boot-order = &emmc, &sdmmc;
	};

};

&pinctrl {
	u-boot,dm-pre-reloc;
};

&service_msch {
	u-boot,dm-pre-reloc;
};

&dmc {
	u-boot,dm-pre-reloc;

	/*
	 * Validation of throughput using SPEC2000 shows the following
	 * relative performance for the different memory schedules:
	 *  - CBDR: 30.1
	 *  - CBRD: 29.8
	 *  - CRBD: 29.9
	 * Note that the best performance for any given application workload
	 * may vary from the default configured here (e.g. 164.gzip is fastest
	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
	 *
	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
	 * details on the 'rockchip,memory-schedule' property and how it
	 * affects the physical-address to device-address mapping.
	 */
	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
	rockchip,ddr-frequency = <800000000>;
	rockchip,ddr-speed-bin = <DDR3_1600K>;

	status = "okay";
};

&pmugrf {
	u-boot,dm-pre-reloc;
};

&sgrf {
        u-boot,dm-pre-reloc;
};

&cru {
	u-boot,dm-pre-reloc;
};

&grf {
	u-boot,dm-pre-reloc;
};

&uart0 {
	u-boot,dm-pre-reloc;
};

&emmc {
	u-boot,dm-pre-reloc;
};

&sdmmc {
	u-boot,dm-pre-reloc;
};

&spi1 {
	u-boot,dm-pre-reloc;

	spiflash: w25q32dw@0 {
		u-boot,dm-pre-reloc;
	};
};