blob: 4b2dd82b67e0827d8e517a8e84a404c4b5c8a2bc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
*
* Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
*/
/dts-v1/;
#include "rk3399-rock960.dtsi"
/ {
model = "96boards RK3399 Ficus";
compatible = "vamrs,ficus", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc3v3_sys>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
};
&pinctrl {
gmac {
rgmii_sleep_pins: rgmii-sleep-pins {
rockchip,pins =
<3 15 RK_FUNC_GPIO &pcfg_output_low>;
};
};
pcie {
pcie_drv: pcie-drv {
rockchip,pins =
<1 24 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&vcc3v3_pcie {
gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
};
&vcc5v0_host {
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
};
|
