summaryrefslogtreecommitdiff
path: root/arch/arm/dts/s900.dtsi
blob: 2bbb30a5a8657101b13e4ece22fe930f0cd5b542 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
// SPDX-License-Identifier: GPL-2.0+
//
// Device Tree Source for Actions Semi S900 SoC
//
// Copyright (C) 2015 Actions Semi Co., Ltd.
// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

/dts-v1/;
#include <dt-bindings/clock/s900_cmu.h>

/ {
	compatible = "actions,s900";
	#address-cells = <0x2>;
	#size-cells = <0x2>;

	losc: losc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		#clock-cells = <0>;
	};

	diff24M: diff24M {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
	};

	soc {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		uart5: serial@e012a000 {
			u-boot,dm-pre-reloc;
			compatible = "actions,s900-serial";
			reg = <0x0 0xe012a000 0x0 0x1000>;
			clocks = <&cmu CLOCK_UART5>;
			status = "disabled";
		};

		cmu: clock-controller@e0160000 {
			u-boot,dm-pre-reloc;
			compatible = "actions,s900-cmu";
			reg = <0x0 0xe0160000 0x0 0x1000>;
			clocks = <&losc>, <&diff24M>;
			clock-names = "losc", "diff24M";
			#clock-cells = <1>;
		};
	};
};