summaryrefslogtreecommitdiff
path: root/arch/arm/dts/stm32mp15-u-boot.dtsi
blob: 1279589a563246d1b55c9835750e291d8fef8afc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright : STMicroelectronics 2018
 */

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
		gpio25 = &gpioz;
		pinctrl0 = &pinctrl;
		pinctrl1 = &pinctrl_z;
	};

	clocks {
		u-boot,dm-pre-reloc;
	};

	/* need PSCI for sysreset during board_f */
	psci {
		u-boot,dm-pre-proper;
	};

	reboot {
		u-boot,dm-pre-reloc;
	};

	soc {
		u-boot,dm-pre-reloc;

		ddr: ddr@5a003000 {
			u-boot,dm-pre-reloc;

			compatible = "st,stm32mp1-ddr";

			reg = <0x5A003000 0x550
			       0x5A004000 0x234>;

			clocks = <&rcc AXIDCG>,
				 <&rcc DDRC1>,
				 <&rcc DDRC2>,
				 <&rcc DDRPHYC>,
				 <&rcc DDRCAPB>,
				 <&rcc DDRPHYCAPB>;

			clock-names = "axidcg",
				      "ddrc1",
				      "ddrc2",
				      "ddrphyc",
				      "ddrcapb",
				      "ddrphycapb";

			status = "okay";
		};
	};
};

&bsec {
	u-boot,dm-pre-proper;
};

&clk_csi {
	u-boot,dm-pre-reloc;
};

&clk_hsi {
	u-boot,dm-pre-reloc;
};

&clk_hse {
	u-boot,dm-pre-reloc;
};

&clk_lsi {
	u-boot,dm-pre-reloc;
};

&clk_lse {
	u-boot,dm-pre-reloc;
};

&gpioa {
	u-boot,dm-pre-reloc;
};

&gpiob {
	u-boot,dm-pre-reloc;
};

&gpioc {
	u-boot,dm-pre-reloc;
};

&gpiod {
	u-boot,dm-pre-reloc;
};

&gpioe {
	u-boot,dm-pre-reloc;
};

&gpiof {
	u-boot,dm-pre-reloc;
};

&gpiog {
	u-boot,dm-pre-reloc;
};

&gpioh {
	u-boot,dm-pre-reloc;
};

&gpioi {
	u-boot,dm-pre-reloc;
};

&gpioj {
	u-boot,dm-pre-reloc;
};

&gpiok {
	u-boot,dm-pre-reloc;
};

&gpioz {
	u-boot,dm-pre-reloc;
};

&iwdg2 {
	u-boot,dm-pre-reloc;
};

/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
	u-boot,dm-pre-proper;
};

&pinctrl {
	u-boot,dm-pre-reloc;
};

&pinctrl_z {
	u-boot,dm-pre-reloc;
};

&pwr_regulators {
	u-boot,dm-pre-reloc;
};

&rcc {
	u-boot,dm-pre-reloc;
	#address-cells = <1>;
	#size-cells = <0>;
};

&sdmmc1 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&sdmmc2 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&sdmmc3 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&usbotg_hs {
	compatible = "st,stm32mp1-hsotg", "snps,dwc2";
};