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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZCU1275 RevB";
compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
mmc0 = &sdhci1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&dcc {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&uart0 {
status = "okay";
};
&sdhci1 {
status = "okay";
/*
* 1.0 revision has level shifter and this property should be
* removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};
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