blob: 9b56b4e51bf09d1b8c8783f8d4d201fc4650e682 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
|
/*
* (C) Copyright 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __ASM_ARM_ARCH_CLOCK_H_
#define __ASM_ARM_ARCH_CLOCK_H_
#ifndef __ASSEMBLY__
struct exynos4_clock {
unsigned char res1[0x4200];
unsigned int src_leftbus;
unsigned char res2[0x1fc];
unsigned int mux_stat_leftbus;
unsigned char res4[0xfc];
unsigned int div_leftbus;
unsigned char res5[0xfc];
unsigned int div_stat_leftbus;
unsigned char res6[0x1fc];
unsigned int gate_ip_leftbus;
unsigned char res7[0x1fc];
unsigned int clkout_leftbus;
unsigned int clkout_leftbus_div_stat;
unsigned char res8[0x37f8];
unsigned int src_rightbus;
unsigned char res9[0x1fc];
unsigned int mux_stat_rightbus;
unsigned char res10[0xfc];
unsigned int div_rightbus;
unsigned char res11[0xfc];
unsigned int div_stat_rightbus;
unsigned char res12[0x1fc];
unsigned int gate_ip_rightbus;
unsigned char res13[0x1fc];
unsigned int clkout_rightbus;
unsigned int clkout_rightbus_div_stat;
unsigned char res14[0x3608];
unsigned int epll_lock;
unsigned char res15[0xc];
unsigned int vpll_lock;
unsigned char res16[0xec];
unsigned int epll_con0;
unsigned int epll_con1;
unsigned char res17[0x8];
unsigned int vpll_con0;
unsigned int vpll_con1;
unsigned char res18[0xe8];
unsigned int src_top0;
unsigned int src_top1;
unsigned char res19[0x8];
unsigned int src_cam;
unsigned int src_tv;
unsigned int src_mfc;
unsigned int src_g3d;
unsigned int src_image;
unsigned int src_lcd0;
unsigned int src_lcd1;
unsigned int src_maudio;
unsigned int src_fsys;
unsigned char res20[0xc];
unsigned int src_peril0;
unsigned int src_peril1;
unsigned char res21[0xb8];
unsigned int src_mask_top;
unsigned char res22[0xc];
unsigned int src_mask_cam;
unsigned int src_mask_tv;
unsigned char res23[0xc];
unsigned int src_mask_lcd0;
unsigned int src_mask_lcd1;
unsigned int src_mask_maudio;
unsigned int src_mask_fsys;
unsigned char res24[0xc];
unsigned int src_mask_peril0;
unsigned int src_mask_peril1;
unsigned char res25[0xb8];
unsigned int mux_stat_top;
unsigned char res26[0x14];
unsigned int mux_stat_mfc;
unsigned int mux_stat_g3d;
unsigned int mux_stat_image;
unsigned char res27[0xdc];
unsigned int div_top;
unsigned char res28[0xc];
unsigned int div_cam;
unsigned int div_tv;
unsigned int div_mfc;
unsigned int div_g3d;
unsigned int div_image;
unsigned int div_lcd0;
unsigned int div_lcd1;
unsigned int div_maudio;
unsigned int div_fsys0;
unsigned int div_fsys1;
unsigned int div_fsys2;
unsigned int div_fsys3;
unsigned int div_peril0;
unsigned int div_peril1;
unsigned int div_peril2;
unsigned int div_peril3;
unsigned int div_peril4;
unsigned int div_peril5;
unsigned char res29[0x18];
unsigned int div2_ratio;
unsigned char res30[0x8c];
unsigned int div_stat_top;
unsigned char res31[0xc];
unsigned int div_stat_cam;
unsigned int div_stat_tv;
unsigned int div_stat_mfc;
unsigned int div_stat_g3d;
unsigned int div_stat_image;
unsigned int div_stat_lcd0;
unsigned int div_stat_lcd1;
unsigned int div_stat_maudio;
unsigned int div_stat_fsys0;
unsigned int div_stat_fsys1;
unsigned int div_stat_fsys2;
unsigned int div_stat_fsys3;
unsigned int div_stat_peril0;
unsigned int div_stat_peril1;
unsigned int div_stat_peril2;
unsigned int div_stat_peril3;
unsigned int div_stat_peril4;
unsigned int div_stat_peril5;
unsigned char res32[0x18];
unsigned int div2_stat;
unsigned char res33[0x29c];
unsigned int gate_ip_cam;
unsigned int gate_ip_tv;
unsigned int gate_ip_mfc;
unsigned int gate_ip_g3d;
unsigned int gate_ip_image;
unsigned int gate_ip_lcd0;
unsigned int gate_ip_lcd1;
unsigned char res34[0x4];
unsigned int gate_ip_fsys;
unsigned char res35[0x8];
unsigned int gate_ip_gps;
unsigned int gate_ip_peril;
unsigned char res36[0xc];
unsigned int gate_ip_perir;
unsigned char res37[0xc];
unsigned int gate_block;
unsigned char res38[0x8c];
unsigned int clkout_cmu_top;
unsigned int clkout_cmu_top_div_stat;
unsigned char res39[0x37f8];
unsigned int src_dmc;
unsigned char res40[0xfc];
unsigned int src_mask_dmc;
unsigned char res41[0xfc];
unsigned int mux_stat_dmc;
unsigned char res42[0xfc];
unsigned int div_dmc0;
unsigned int div_dmc1;
unsigned char res43[0xf8];
unsigned int div_stat_dmc0;
unsigned int div_stat_dmc1;
unsigned char res44[0x2f8];
unsigned int gate_ip_dmc;
unsigned char res45[0xfc];
unsigned int clkout_cmu_dmc;
unsigned int clkout_cmu_dmc_div_stat;
unsigned char res46[0x5f8];
unsigned int dcgidx_map0;
unsigned int dcgidx_map1;
unsigned int dcgidx_map2;
unsigned char res47[0x14];
unsigned int dcgperf_map0;
unsigned int dcgperf_map1;
unsigned char res48[0x18];
unsigned int dvcidx_map;
unsigned char res49[0x1c];
unsigned int freq_cpu;
unsigned int freq_dpm;
unsigned char res50[0x18];
unsigned int dvsemclk_en;
unsigned int maxperf;
unsigned char res51[0x2f78];
unsigned int apll_lock;
unsigned char res52[0x4];
unsigned int mpll_lock;
unsigned char res53[0xf4];
unsigned int apll_con0;
unsigned int apll_con1;
unsigned int mpll_con0;
unsigned int mpll_con1;
unsigned char res54[0xf0];
unsigned int src_cpu;
unsigned char res55[0x1fc];
unsigned int mux_stat_cpu;
unsigned char res56[0xfc];
unsigned int div_cpu0;
unsigned int div_cpu1;
unsigned char res57[0xf8];
unsigned int div_stat_cpu0;
unsigned int div_stat_cpu1;
unsigned char res58[0x3f8];
unsigned int clkout_cmu_cpu;
unsigned int clkout_cmu_cpu_div_stat;
unsigned char res59[0x5f8];
unsigned int armclk_stopctrl;
unsigned int atclk_stopctrl;
unsigned char res60[0x8];
unsigned int parityfail_status;
unsigned int parityfail_clear;
unsigned char res61[0xe8];
unsigned int apll_con0_l8;
unsigned int apll_con0_l7;
unsigned int apll_con0_l6;
unsigned int apll_con0_l5;
unsigned int apll_con0_l4;
unsigned int apll_con0_l3;
unsigned int apll_con0_l2;
unsigned int apll_con0_l1;
unsigned int iem_control;
unsigned char res62[0xdc];
unsigned int apll_con1_l8;
unsigned int apll_con1_l7;
unsigned int apll_con1_l6;
unsigned int apll_con1_l5;
unsigned int apll_con1_l4;
unsigned int apll_con1_l3;
unsigned int apll_con1_l2;
unsigned int apll_con1_l1;
unsigned char res63[0xe0];
unsigned int div_iem_l8;
unsigned int div_iem_l7;
unsigned int div_iem_l6;
unsigned int div_iem_l5;
unsigned int div_iem_l4;
unsigned int div_iem_l3;
unsigned int div_iem_l2;
unsigned int div_iem_l1;
};
struct exynos4x12_clock {
unsigned char res1[0x4200];
unsigned int src_leftbus;
unsigned char res2[0x1fc];
unsigned int mux_stat_leftbus;
unsigned char res3[0xfc];
unsigned int div_leftbus;
unsigned char res4[0xfc];
unsigned int div_stat_leftbus;
unsigned char res5[0x1fc];
unsigned int gate_ip_leftbus;
unsigned char res6[0x12c];
unsigned int gate_ip_image;
unsigned char res7[0xcc];
unsigned int clkout_leftbus;
unsigned int clkout_leftbus_div_stat;
unsigned char res8[0x37f8];
unsigned int src_rightbus;
unsigned char res9[0x1fc];
unsigned int mux_stat_rightbus;
unsigned char res10[0xfc];
unsigned int div_rightbus;
unsigned char res11[0xfc];
unsigned int div_stat_rightbus;
unsigned char res12[0x1fc];
unsigned int gate_ip_rightbus;
unsigned char res13[0x15c];
unsigned int gate_ip_perir;
unsigned char res14[0x9c];
unsigned int clkout_rightbus;
unsigned int clkout_rightbus_div_stat;
unsigned char res15[0x3608];
unsigned int epll_lock;
unsigned char res16[0xc];
unsigned int vpll_lock;
unsigned char res17[0xec];
unsigned int epll_con0;
unsigned int epll_con1;
unsigned int epll_con2;
unsigned char res18[0x4];
unsigned int vpll_con0;
unsigned int vpll_con1;
unsigned int vpll_con2;
unsigned char res19[0xe4];
unsigned int src_top0;
unsigned int src_top1;
unsigned char res20[0x8];
unsigned int src_cam;
unsigned int src_tv;
unsigned int src_mfc;
unsigned int src_g3d;
unsigned char res21[0x4];
unsigned int src_lcd;
unsigned int src_isp;
unsigned int src_maudio;
unsigned int src_fsys;
unsigned char res22[0xc];
unsigned int src_peril0;
unsigned int src_peril1;
unsigned int src_cam1;
unsigned char res23[0xb4];
unsigned int src_mask_top;
unsigned char res24[0xc];
unsigned int src_mask_cam;
unsigned int src_mask_tv;
unsigned char res25[0xc];
unsigned int src_mask_lcd;
unsigned int src_mask_isp;
unsigned int src_mask_maudio;
unsigned int src_mask_fsys;
unsigned char res26[0xc];
unsigned int src_mask_peril0;
unsigned int src_mask_peril1;
unsigned char res27[0xb8];
unsigned int mux_stat_top0;
unsigned int mux_stat_top1;
unsigned char res28[0x10];
unsigned int mux_stat_mfc;
unsigned int mux_stat_g3d;
unsigned char res29[0x28];
unsigned int mux_stat_cam1;
unsigned char res30[0xb4];
unsigned int div_top;
unsigned char res31[0xc];
unsigned int div_cam;
unsigned int div_tv;
unsigned int div_mfc;
unsigned int div_g3d;
unsigned char res32[0x4];
unsigned int div_lcd;
unsigned int div_isp;
unsigned int div_maudio;
unsigned int div_fsys0;
unsigned int div_fsys1;
unsigned int div_fsys2;
unsigned int div_fsys3;
unsigned int div_peril0;
unsigned int div_peril1;
unsigned int div_peril2;
unsigned int div_peril3;
unsigned int div_peril4;
unsigned int div_peril5;
unsigned int div_cam1;
unsigned char res33[0x14];
unsigned int div2_ratio;
unsigned char res34[0x8c];
unsigned int div_stat_top;
unsigned char res35[0xc];
unsigned int div_stat_cam;
unsigned int div_stat_tv;
unsigned int div_stat_mfc;
unsigned int div_stat_g3d;
unsigned char res36[0x4];
unsigned int div_stat_lcd;
unsigned int div_stat_isp;
unsigned int div_stat_maudio;
unsigned int div_stat_fsys0;
unsigned int div_stat_fsys1;
unsigned int div_stat_fsys2;
unsigned int div_stat_fsys3;
unsigned int div_stat_peril0;
unsigned int div_stat_peril1;
unsigned int div_stat_peril2;
unsigned int div_stat_peril3;
unsigned int div_stat_peril4;
unsigned int div_stat_peril5;
unsigned int div_stat_cam1;
unsigned char res37[0x14];
unsigned int div2_stat;
unsigned char res38[0x29c];
unsigned int gate_ip_cam;
unsigned int gate_ip_tv;
unsigned int gate_ip_mfc;
unsigned int gate_ip_g3d;
unsigned char res39[0x4];
unsigned int gate_ip_lcd;
unsigned int gate_ip_isp;
unsigned char res40[0x4];
unsigned int gate_ip_fsys;
unsigned char res41[0x8];
unsigned int gate_ip_gps;
unsigned int gate_ip_peril;
unsigned char res42[0xc];
unsigned char res43[0x4];
unsigned char res44[0xc];
unsigned int gate_block;
unsigned char res45[0x8c];
unsigned int clkout_cmu_top;
unsigned int clkout_cmu_top_div_stat;
unsigned char res46[0x3600];
unsigned int mpll_lock;
unsigned char res47[0xfc];
unsigned int mpll_con0;
unsigned int mpll_con1;
unsigned char res48[0xf0];
unsigned int src_dmc;
unsigned char res49[0xfc];
unsigned int src_mask_dmc;
unsigned char res50[0xfc];
unsigned int mux_stat_dmc;
unsigned char res51[0xfc];
unsigned int div_dmc0;
unsigned int div_dmc1;
unsigned char res52[0xf8];
unsigned int div_stat_dmc0;
unsigned int div_stat_dmc1;
unsigned char res53[0xf8];
unsigned int gate_bus_dmc0;
unsigned int gate_bus_dmc1;
unsigned char res54[0x1f8];
unsigned int gate_ip_dmc0;
unsigned int gate_ip_dmc1;
unsigned char res55[0xf8];
unsigned int clkout_cmu_dmc;
unsigned int clkout_cmu_dmc_div_stat;
unsigned char res56[0x5f8];
unsigned int dcgidx_map0;
unsigned int dcgidx_map1;
unsigned int dcgidx_map2;
unsigned char res57[0x14];
unsigned int dcgperf_map0;
unsigned int dcgperf_map1;
unsigned char res58[0x18];
unsigned int dvcidx_map;
unsigned char res59[0x1c];
unsigned int freq_cpu;
unsigned int freq_dpm;
unsigned char res60[0x18];
unsigned int dvsemclk_en;
unsigned int maxperf;
unsigned char res61[0x8];
unsigned int dmc_freq_ctrl;
unsigned int dmc_pause_ctrl;
unsigned int dddrphy_lock_ctrl;
unsigned int c2c_state;
unsigned char res62[0x2f60];
unsigned int apll_lock;
unsigned char res63[0x8];
unsigned char res64[0xf4];
unsigned int apll_con0;
unsigned int apll_con1;
unsigned char res65[0xf8];
unsigned int src_cpu;
unsigned char res66[0x1fc];
unsigned int mux_stat_cpu;
unsigned char res67[0xfc];
unsigned int div_cpu0;
unsigned int div_cpu1;
unsigned char res68[0xf8];
unsigned int div_stat_cpu0;
unsigned int div_stat_cpu1;
unsigned char res69[0x2f8];
unsigned int clk_gate_ip_cpu;
unsigned char res70[0xfc];
unsigned int clkout_cmu_cpu;
unsigned int clkout_cmu_cpu_div_stat;
unsigned char res71[0x5f8];
unsigned int armclk_stopctrl;
unsigned int atclk_stopctrl;
unsigned char res72[0x10];
unsigned char res73[0x8];
unsigned int pwr_ctrl;
unsigned int pwr_ctrl2;
unsigned char res74[0xd8];
unsigned int apll_con0_l8;
unsigned int apll_con0_l7;
unsigned int apll_con0_l6;
unsigned int apll_con0_l5;
unsigned int apll_con0_l4;
unsigned int apll_con0_l3;
unsigned int apll_con0_l2;
unsigned int apll_con0_l1;
unsigned int iem_control;
unsigned char res75[0xdc];
unsigned int apll_con1_l8;
unsigned int apll_con1_l7;
unsigned int apll_con1_l6;
unsigned int apll_con1_l5;
unsigned int apll_con1_l4;
unsigned int apll_con1_l3;
unsigned int apll_con1_l2;
unsigned int apll_con1_l1;
unsigned char res76[0xe0];
unsigned int div_iem_l8;
unsigned int div_iem_l7;
unsigned int div_iem_l6;
unsigned int div_iem_l5;
unsigned int div_iem_l4;
unsigned int div_iem_l3;
unsigned int div_iem_l2;
unsigned int div_iem_l1;
unsigned char res77[0xe0];
unsigned int l2_status;
unsigned char res78[0xc];
unsigned int cpu_status;
unsigned char res79[0xc];
unsigned int ptm_status;
unsigned char res80[0x2edc];
unsigned int div_isp0;
unsigned int div_isp1;
unsigned char res81[0xf8];
unsigned int div_stat_isp0;
unsigned int div_stat_isp1;
unsigned char res82[0x3f8];
unsigned int gate_ip_isp0;
unsigned int gate_ip_isp1;
unsigned char res83[0x1f8];
unsigned int clkout_cmu_isp;
unsigned int clkout_cmu_ispd_div_stat;
unsigned char res84[0xf8];
unsigned int cmu_isp_spar0;
unsigned int cmu_isp_spar1;
unsigned int cmu_isp_spar2;
unsigned int cmu_isp_spar3;
};
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
unsigned int apll_con0;
unsigned int apll_con1;
unsigned char res2[0xf8];
unsigned int src_cpu;
unsigned char res3[0x1fc];
unsigned int mux_stat_cpu;
unsigned char res4[0xfc];
unsigned int div_cpu0;
unsigned int div_cpu1;
unsigned char res5[0xf8];
unsigned int div_stat_cpu0;
unsigned int div_stat_cpu1;
unsigned char res6[0x1f8];
unsigned int gate_sclk_cpu;
unsigned char res7[0x1fc];
unsigned int clkout_cmu_cpu;
unsigned int clkout_cmu_cpu_div_stat;
unsigned char res8[0x5f8];
unsigned int armclk_stopctrl;
unsigned char res9[0x0c];
unsigned int parityfail_status;
unsigned int parityfail_clear;
unsigned char res10[0x8];
unsigned int pwr_ctrl;
unsigned int pwr_ctr2;
unsigned char res11[0xd8];
unsigned int apll_con0_l8;
unsigned int apll_con0_l7;
unsigned int apll_con0_l6;
unsigned int apll_con0_l5;
unsigned int apll_con0_l4;
unsigned int apll_con0_l3;
unsigned int apll_con0_l2;
unsigned int apll_con0_l1;
unsigned int iem_control;
unsigned char res12[0xdc];
unsigned int apll_con1_l8;
unsigned int apll_con1_l7;
unsigned int apll_con1_l6;
unsigned int apll_con1_l5;
unsigned int apll_con1_l4;
unsigned int apll_con1_l3;
unsigned int apll_con1_l2;
unsigned int apll_con1_l1;
unsigned char res13[0xe0];
unsigned int div_iem_l8;
unsigned int div_iem_l7;
unsigned int div_iem_l6;
unsigned int div_iem_l5;
unsigned int div_iem_l4;
unsigned int div_iem_l3;
unsigned int div_iem_l2;
unsigned int div_iem_l1;
unsigned char res14[0x2ce0];
unsigned int mpll_lock;
unsigned char res15[0xfc];
unsigned int mpll_con0;
unsigned int mpll_con1;
unsigned char res16[0xf8];
unsigned int src_core0;
unsigned int src_core1;
unsigned char res17[0xf8];
unsigned int src_mask_core;
unsigned char res18[0x100];
unsigned int mux_stat_core1;
unsigned char res19[0xf8];
unsigned int div_core0;
unsigned int div_core1;
unsigned int div_sysrgt;
unsigned char res20[0xf4];
unsigned int div_stat_core0;
unsigned int div_stat_core1;
unsigned int div_stat_sysrgt;
unsigned char res21[0x2f4];
unsigned int gate_ip_core;
unsigned int gate_ip_sysrgt;
unsigned char res22[0x8];
unsigned int c2c_monitor;
unsigned char res23[0xec];
unsigned int clkout_cmu_core;
unsigned int clkout_cmu_core_div_stat;
unsigned char res24[0x5f8];
unsigned int dcgidx_map0;
unsigned int dcgidx_map1;
unsigned int dcgidx_map2;
unsigned char res25[0x14];
unsigned int dcgperf_map0;
unsigned int dcgperf_map1;
unsigned char res26[0x18];
unsigned int dvcidx_map;
unsigned char res27[0x1c];
unsigned int freq_cpu;
unsigned int freq_dpm;
unsigned char res28[0x18];
unsigned int dvsemclk_en;
unsigned int maxperf;
unsigned char res29[0xf78];
unsigned int c2c_config;
unsigned char res30[0x24fc];
unsigned int div_acp;
unsigned char res31[0xfc];
unsigned int div_stat_acp;
unsigned char res32[0x1fc];
unsigned int gate_ip_acp;
unsigned char res33[0xfc];
unsigned int div_syslft;
unsigned char res34[0xc];
unsigned int div_stat_syslft;
unsigned char res35[0x1c];
unsigned int gate_ip_syslft;
unsigned char res36[0xcc];
unsigned int clkout_cmu_acp;
unsigned int clkout_cmu_acp_div_stat;
unsigned char res37[0x8];
unsigned int ufmc_config;
unsigned char res38[0x38ec];
unsigned int div_isp0;
unsigned int div_isp1;
unsigned int div_isp2;
unsigned char res39[0xf4];
unsigned int div_stat_isp0;
unsigned int div_stat_isp1;
unsigned int div_stat_isp2;
unsigned char res40[0x3f4];
unsigned int gate_ip_isp0;
unsigned int gate_ip_isp1;
unsigned char res41[0xf8];
unsigned int gate_sclk_isp;
unsigned char res42[0xc];
unsigned int mcuisp_pwr_ctrl;
unsigned char res43[0xec];
unsigned int clkout_cmu_isp;
unsigned int clkout_cmu_isp_div_stat;
unsigned char res44[0x3618];
unsigned int cpll_lock;
unsigned char res45[0xc];
unsigned int epll_lock;
unsigned char res46[0xc];
unsigned int vpll_lock;
unsigned char res47[0xc];
unsigned int gpll_lock;
unsigned char res48[0xcc];
unsigned int cpll_con0;
unsigned int cpll_con1;
unsigned char res49[0x8];
unsigned int epll_con0;
unsigned int epll_con1;
unsigned int epll_con2;
unsigned char res50[0x4];
unsigned int vpll_con0;
unsigned int vpll_con1;
unsigned int vpll_con2;
unsigned char res51[0x4];
unsigned int gpll_con0;
unsigned int gpll_con1;
unsigned char res52[0xb8];
unsigned int src_top0;
unsigned int src_top1;
unsigned int src_top2;
unsigned int src_top3;
unsigned int src_gscl;
unsigned char res53[0x8];
unsigned int src_disp1_0;
unsigned char res54[0x10];
unsigned int src_mau;
unsigned int src_fsys;
unsigned int src_gen;
unsigned char res55[0x4];
unsigned int src_peric0;
unsigned int src_peric1;
unsigned char res56[0x18];
unsigned int sclk_src_isp;
unsigned char res57[0x9c];
unsigned int src_mask_top;
unsigned char res58[0xc];
unsigned int src_mask_gscl;
unsigned char res59[0x8];
unsigned int src_mask_disp1_0;
unsigned char res60[0x4];
unsigned int src_mask_mau;
unsigned char res61[0x8];
unsigned int src_mask_fsys;
unsigned int src_mask_gen;
unsigned char res62[0x8];
unsigned int src_mask_peric0;
unsigned int src_mask_peric1;
unsigned char res63[0x18];
unsigned int src_mask_isp;
unsigned char res67[0x9c];
unsigned int mux_stat_top0;
unsigned int mux_stat_top1;
unsigned int mux_stat_top2;
unsigned int mux_stat_top3;
unsigned char res68[0xf0];
unsigned int div_top0;
unsigned int div_top1;
unsigned char res69[0x8];
unsigned int div_gscl;
unsigned char res70[0x8];
unsigned int div_disp1_0;
unsigned char res71[0xc];
unsigned int div_gen;
unsigned char res72[0x4];
unsigned int div_mau;
unsigned int div_fsys0;
unsigned int div_fsys1;
unsigned int div_fsys2;
unsigned char res73[0x4];
unsigned int div_peric0;
unsigned int div_peric1;
unsigned int div_peric2;
unsigned int div_peric3;
unsigned int div_peric4;
unsigned int div_peric5;
unsigned char res74[0x10];
unsigned int sclk_div_isp;
unsigned char res75[0xc];
unsigned int div2_ratio0;
unsigned int div2_ratio1;
unsigned char res76[0x8];
unsigned int div4_ratio;
unsigned char res77[0x6c];
unsigned int div_stat_top0;
unsigned int div_stat_top1;
unsigned char res78[0x8];
unsigned int div_stat_gscl;
unsigned char res79[0x8];
unsigned int div_stat_disp1_0;
unsigned char res80[0xc];
unsigned int div_stat_gen;
unsigned char res81[0x4];
unsigned int div_stat_mau;
unsigned int div_stat_fsys0;
unsigned int div_stat_fsys1;
unsigned int div_stat_fsys2;
unsigned char res82[0x4];
unsigned int div_stat_peric0;
unsigned int div_stat_peric1;
unsigned int div_stat_peric2;
unsigned int div_stat_peric3;
unsigned int div_stat_peric4;
unsigned int div_stat_peric5;
unsigned char res83[0x10];
unsigned int sclk_div_stat_isp;
unsigned char res84[0xc];
unsigned int div2_stat0;
unsigned int div2_stat1;
unsigned char res85[0x8];
unsigned int div4_stat;
unsigned char res86[0x184];
unsigned int gate_top_sclk_disp1;
unsigned int gate_top_sclk_gen;
unsigned char res87[0xc];
unsigned int gate_top_sclk_mau;
unsigned int gate_top_sclk_fsys;
unsigned char res88[0xc];
unsigned int gate_top_sclk_peric;
unsigned char res89[0x1c];
unsigned int gate_top_sclk_isp;
unsigned char res90[0xac];
unsigned int gate_ip_gscl;
unsigned char res91[0x4];
unsigned int gate_ip_disp1;
unsigned int gate_ip_mfc;
unsigned int gate_ip_g3d;
unsigned int gate_ip_gen;
unsigned char res92[0xc];
unsigned int gate_ip_fsys;
unsigned char res93[0x8];
unsigned int gate_ip_peric;
unsigned char res94[0xc];
unsigned int gate_ip_peris;
unsigned char res95[0x1c];
unsigned int gate_block;
unsigned char res96[0x1c];
unsigned int mcuiop_pwr_ctrl;
unsigned char res97[0x5c];
unsigned int clkout_cmu_top;
unsigned int clkout_cmu_top_div_stat;
unsigned char res98[0x37f8];
unsigned int src_lex;
unsigned char res99[0x1fc];
unsigned int mux_stat_lex;
unsigned char res100[0xfc];
unsigned int div_lex;
unsigned char res101[0xfc];
unsigned int div_stat_lex;
unsigned char res102[0x1fc];
unsigned int gate_ip_lex;
unsigned char res103[0x1fc];
unsigned int clkout_cmu_lex;
unsigned int clkout_cmu_lex_div_stat;
unsigned char res104[0x3af8];
unsigned int div_r0x;
unsigned char res105[0xfc];
unsigned int div_stat_r0x;
unsigned char res106[0x1fc];
unsigned int gate_ip_r0x;
unsigned char res107[0x1fc];
unsigned int clkout_cmu_r0x;
unsigned int clkout_cmu_r0x_div_stat;
unsigned char res108[0x3af8];
unsigned int div_r1x;
unsigned char res109[0xfc];
unsigned int div_stat_r1x;
unsigned char res110[0x1fc];
unsigned int gate_ip_r1x;
unsigned char res111[0x1fc];
unsigned int clkout_cmu_r1x;
unsigned int clkout_cmu_r1x_div_stat;
unsigned char res112[0x3608];
unsigned int bpll_lock;
unsigned char res113[0xfc];
unsigned int bpll_con0;
unsigned int bpll_con1;
unsigned char res114[0xe8];
unsigned int src_cdrex;
unsigned char res115[0x1fc];
unsigned int mux_stat_cdrex;
unsigned char res116[0xfc];
unsigned int div_cdrex;
unsigned char res117[0xfc];
unsigned int div_stat_cdrex;
unsigned char res118[0x2fc];
unsigned int gate_ip_cdrex;
unsigned char res119[0x10];
unsigned int dmc_freq_ctrl;
unsigned char res120[0x4];
unsigned int drex2_pause;
unsigned char res121[0xe0];
unsigned int clkout_cmu_cdrex;
unsigned int clkout_cmu_cdrex_div_stat;
unsigned char res122[0x8];
unsigned int lpddr3phy_ctrl;
unsigned int lpddr3phy_con0;
unsigned int lpddr3phy_con1;
unsigned int lpddr3phy_con2;
unsigned int lpddr3phy_con3;
unsigned int pll_div2_sel;
unsigned char res123[0xf5d8];
};
/* structure for epll configuration used in audio clock configuration */
struct set_epll_con_val {
unsigned int freq_out; /* frequency out */
unsigned int en_lock_det; /* enable lock detect */
unsigned int m_div; /* m divider value */
unsigned int p_div; /* p divider value */
unsigned int s_div; /* s divider value */
unsigned int k_dsm; /* k value of delta signal modulator */
};
#endif
#define MPLL_FOUT_SEL_SHIFT 4
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
#define TIMEOUT_EPLL_LOCK 1000
#define AUDIO_0_RATIO_MASK 0x0f
#define AUDIO_1_RATIO_MASK 0x0f
#define AUDIO1_SEL_MASK 0xf
#define CLK_SRC_SCLK_EPLL 0x7
/* CON0 bit-fields */
#define EPLL_CON0_MDIV_MASK 0x1ff
#define EPLL_CON0_PDIV_MASK 0x3f
#define EPLL_CON0_SDIV_MASK 0x7
#define EPLL_CON0_MDIV_SHIFT 16
#define EPLL_CON0_PDIV_SHIFT 8
#define EPLL_CON0_SDIV_SHIFT 0
#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
#define EPLL_CON0_LOCK_DET_EN_MASK 1
#define MPLL_FOUT_SEL_MASK 0x1
#define BPLL_FOUT_SEL_SHIFT 0
#define BPLL_FOUT_SEL_MASK 0x1
#endif
|
