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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
/* MMDC P0/P1 Registers */
struct mmdc_p_regs {
u32 mdctl;
u32 mdpdc;
u32 mdotc;
u32 mdcfg0;
u32 mdcfg1;
u32 mdcfg2;
u32 mdmisc;
u32 mdscr;
u32 mdref;
u32 res1[2];
u32 mdrwd;
u32 mdor;
u32 res2[3];
u32 mdasp;
u32 res3[240];
u32 mapsr;
u32 res4[254];
u32 mpzqhwctrl;
u32 res5[2];
u32 mpwldectrl0;
u32 mpwldectrl1;
u32 res6;
u32 mpodtctrl;
u32 mprddqby0dl;
u32 mprddqby1dl;
u32 mprddqby2dl;
u32 mprddqby3dl;
u32 res7[4];
u32 mpdgctrl0;
u32 mpdgctrl1;
u32 res8;
u32 mprddlctl;
u32 res9;
u32 mpwrdlctl;
u32 res10[25];
u32 mpmur0;
};
/*
* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
*/
#define MX6DQ_IOM_DDR_BASE 0x020e0500
struct mx6dq_iomux_ddr_regs {
u32 res1[3];
u32 dram_sdqs5;
u32 dram_dqm5;
u32 dram_dqm4;
u32 dram_sdqs4;
u32 dram_sdqs3;
u32 dram_dqm3;
u32 dram_sdqs2;
u32 dram_dqm2;
u32 res2[16];
u32 dram_cas;
u32 res3[2];
u32 dram_ras;
u32 dram_reset;
u32 res4[2];
u32 dram_sdclk_0;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdclk_1;
u32 dram_sdcke1;
u32 dram_sdodt0;
u32 dram_sdodt1;
u32 res5;
u32 dram_sdqs0;
u32 dram_dqm0;
u32 dram_sdqs1;
u32 dram_dqm1;
u32 dram_sdqs6;
u32 dram_dqm6;
u32 dram_sdqs7;
u32 dram_dqm7;
};
#define MX6DQ_IOM_GRP_BASE 0x020e0700
struct mx6dq_iomux_grp_regs {
u32 res1[18];
u32 grp_b7ds;
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 res2;
u32 grp_ddrpke;
u32 res3[6];
u32 grp_ddrmode;
u32 res4[3];
u32 grp_b0ds;
u32 grp_b1ds;
u32 grp_ctlds;
u32 res5;
u32 grp_b2ds;
u32 grp_ddr_type;
u32 grp_b3ds;
u32 grp_b4ds;
u32 grp_b5ds;
u32 grp_b6ds;
};
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
u32 dram_cas;
u32 res2[2];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_dqm4;
u32 dram_dqm5;
u32 dram_dqm6;
u32 dram_dqm7;
u32 dram_ras;
u32 dram_reset;
u32 res3[2];
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdclk_1;
u32 dram_sdodt0;
u32 dram_sdodt1;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_sdqs4;
u32 dram_sdqs5;
u32 dram_sdqs6;
u32 dram_sdqs7;
};
#define MX6SDL_IOM_GRP_BASE 0x020e0700
struct mx6sdl_iomux_grp_regs {
u32 res1[18];
u32 grp_b7ds;
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 res2[2];
u32 grp_ddrmode;
u32 grp_b0ds;
u32 res3;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
u32 grp_b4ds;
u32 grp_b5ds;
u32 res4;
u32 grp_b6ds;
};
#endif /* CONFIG_SPL_BUILD */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
#define MX6_MMDC_P0_MDOTC 0x021b0008
#define MX6_MMDC_P0_MDCFG0 0x021b000c
#define MX6_MMDC_P0_MDCFG1 0x021b0010
#define MX6_MMDC_P0_MDCFG2 0x021b0014
#define MX6_MMDC_P0_MDMISC 0x021b0018
#define MX6_MMDC_P0_MDSCR 0x021b001c
#define MX6_MMDC_P0_MDREF 0x021b0020
#define MX6_MMDC_P0_MDRWD 0x021b002c
#define MX6_MMDC_P0_MDOR 0x021b0030
#define MX6_MMDC_P0_MDASP 0x021b0040
#define MX6_MMDC_P0_MAPSR 0x021b0404
#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
#define MX6_MMDC_P1_MDPDC 0x021b4004
#define MX6_MMDC_P1_MDOTC 0x021b4008
#define MX6_MMDC_P1_MDCFG0 0x021b400c
#define MX6_MMDC_P1_MDCFG1 0x021b4010
#define MX6_MMDC_P1_MDCFG2 0x021b4014
#define MX6_MMDC_P1_MDMISC 0x021b4018
#define MX6_MMDC_P1_MDSCR 0x021b401c
#define MX6_MMDC_P1_MDREF 0x021b4020
#define MX6_MMDC_P1_MDRWD 0x021b402c
#define MX6_MMDC_P1_MDOR 0x021b4030
#define MX6_MMDC_P1_MDASP 0x021b4040
#define MX6_MMDC_P1_MAPSR 0x021b4404
#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */
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