blob: ccc8fa32c49df2244e7d6ff67b994824722ec3f4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/*
* (C) Copyright 2014
* Chen-Yu Tsai <wens@csie.org>
*
* Watchdog register definitions
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_WATCHDOG_H_
#define _SUNXI_WATCHDOG_H_
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
struct sunxi_wdog {
u32 ctl; /* 0x00 */
u32 mode; /* 0x04 */
u32 res[2];
};
#else
#define WDT_CFG_RESET (0x1)
#define WDT_MODE_EN (0x1)
struct sunxi_wdog {
u32 irq_en; /* 0x00 */
u32 irq_sta; /* 0x04 */
u32 res1[2];
u32 ctl; /* 0x10 */
u32 cfg; /* 0x14 */
u32 mode; /* 0x18 */
u32 res2;
};
#endif
#endif /* _SUNXI_WATCHDOG_H_ */
|
