blob: 2e85d842c04fbb56dc68f2900afca6b697d26e10 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Based on:
*
* ----------------------------------------------------------------------------
*
* dm644x_emac.h
*
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
*
* Copyright (C) 2005 Texas Instruments.
*
* ----------------------------------------------------------------------------
*
* Modifications:
* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
*/
#ifndef _DM644X_EMAC_H_
#define _DM644X_EMAC_H_
#include <asm/arch/hardware.h>
#ifdef CONFIG_SOC_DM365
#define EMAC_BASE_ADDR (0x01d07000)
#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
#define DAVINCI_EMAC_VERSION2
#elif defined(CONFIG_SOC_DA8XX)
#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
#define DAVINCI_EMAC_VERSION2
#else
#define EMAC_BASE_ADDR (0x01c80000)
#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
#define EMAC_MDIO_BASE_ADDR (0x01c84000)
#endif
#ifdef CONFIG_SOC_DM646X
#define DAVINCI_EMAC_VERSION2
#define DAVINCI_EMAC_GIG_ENABLE
#endif
#ifdef CONFIG_SOC_DM646X
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 76500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
#elif defined(CONFIG_SOC_DM365)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 121500000
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
#elif defined(CONFIG_SOC_DA8XX)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#else
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#endif
#endif /* _DM644X_EMAC_H_ */
|
