1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
|
// SPDX-License-Identifier: GPL-2.0+
/*
* K3: Architecture initialization
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#include <common.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
#include "common.h"
#include <dm.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
{
/* Translate the base address */
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
/* Unlock the requested partition if locked using two-step sequence */
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
}
static void ctrl_mmr_unlock(void)
{
/* Unlock all WKUP_CTRL_MMR0 module registers */
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
/* Unlock all MCU_CTRL_MMR0 module registers */
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
/* Unlock all CTRL_MMR0 module registers */
mmr_unlock(CTRL_MMR0_BASE, 0);
mmr_unlock(CTRL_MMR0_BASE, 1);
mmr_unlock(CTRL_MMR0_BASE, 2);
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 6);
mmr_unlock(CTRL_MMR0_BASE, 7);
}
static void store_boot_index_from_rom(void)
{
u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
*boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
}
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_AM654_DDRSS)
struct udevice *dev;
int ret;
#endif
/*
* Cannot delay this further as there is a chance that
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
*/
store_boot_index_from_rom();
/* Make all control module registers accessible */
ctrl_mmr_unlock();
#ifdef CONFIG_CPU_V7R
setup_k3_mpu_regions();
#endif
/* Init DM early in-order to invoke system controller */
spl_early_init();
/* Prepare console output */
preloader_console_init();
#ifdef CONFIG_K3_AM654_DDRSS
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#endif
}
u32 spl_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SUPPORT_EMMC_BOOT)
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
/* eMMC boot0 mode is only supported for primary boot */
if (bootindex == K3_PRIMARY_BOOTMODE &&
bootmode == BOOT_DEVICE_MMC1)
return MMCSD_MODE_EMMCBOOT;
#endif
/* Everything else use filesystem if available */
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_EXT_SUPPORT)
return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
}
static u32 __get_backup_bootmedia(u32 devstat)
{
u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
switch (bkup_boot) {
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_USB;
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC2:
{
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
if (port == 0x0)
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_MMC2;
}
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_HYPERFLASH:
return BOOT_DEVICE_HYPERFLASH;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
};
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 devstat)
{
u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
bootmode = BOOT_DEVICE_SPI;
if (bootmode == BOOT_DEVICE_MMC2) {
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
if (port == 0x0)
bootmode = BOOT_DEVICE_MMC1;
} else if (bootmode == BOOT_DEVICE_MMC1) {
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
if (port == 0x1)
bootmode = BOOT_DEVICE_MMC2;
}
return bootmode;
}
u32 spl_boot_device(void)
{
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
if (bootindex == K3_PRIMARY_BOOTMODE)
return __get_primary_bootmedia(devstat);
else
return __get_backup_bootmedia(devstat);
}
#endif
#ifndef CONFIG_SYSRESET
void reset_cpu(ulong ignored)
{
}
#endif
|