blob: c3ca8cdf3babc4a241f14b7eec77a9d1fb3f57db (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016-2017 Intel Corporation
*/
#ifndef _MISC_H_
#define _MISC_H_
#include <asm/sections.h>
void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
struct bsel {
const char *mode;
const char *name;
};
extern struct bsel bsel_str[];
#ifdef CONFIG_FPGA
void socfpga_fpga_add(void *fpga_desc);
#else
inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
void socfpga_sdram_remap_zero(void);
static inline bool socfpga_is_booting_from_fpga(void)
{
if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
return true;
return false;
}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
void socfpga_init_security_policies(void);
void socfpga_sdram_remap_zero(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
#endif /* _MISC_H_ */
|
