blob: e047f678211d43555bd2d3fa9b9f823b54ccaba4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*/
/* Tegra vpr routines */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/mc.h>
#include <asm/arch-tegra/ap.h>
#include <fdt_support.h>
static bool _configured;
void tegra_gpu_config(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
#endif
{
/* Turn VPR off */
writel(0, &mc->mc_video_protect_size_mb);
writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
&mc->mc_video_protect_reg_ctrl);
/* read back to ensure the write went through */
readl(&mc->mc_video_protect_reg_ctrl);
}
debug("configured VPR\n");
_configured = true;
}
#if defined(CONFIG_OF_LIBFDT)
int tegra_gpu_enable_node(void *blob, const char *compat)
{
int offset;
if (!_configured)
return 0;
offset = fdt_node_offset_by_compatible(blob, -1, compat);
while (offset != -FDT_ERR_NOTFOUND) {
fdt_status_okay(blob, offset);
offset = fdt_node_offset_by_compatible(blob, offset, compat);
}
return 0;
}
#endif
|
