blob: 1ac52d11f34ad2854d660fffbe4c018772596c66 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
{
u32 tmp;
/*
* Set DPLL SSC parameters for DPLLCTRL3
* [23] DIVN_TEST 0x1
* [22:16] DIVN 0x50
* [10] FREFSEL_TEST 0x1
* [9:8] FREFSEL 0x2
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
tmp = readl(sc_base + SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
writel(tmp, sc_base + SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
* <-1%> <-2%>
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
writel(tmp, sc_base + SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
* [31:29] SSC_STEP 0
* [27] SSC_REG_REF 1
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
tmp = readl(sc_base + SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
return 0;
}
|
