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/*
* Copyright (C) 2016 Socionext Inc.
*/
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
#define PHY_SCL_DATA_0 0x00000104
#define PHY_SCL_DATA_1 0x00000108
#define PHY_SCL_LATENCY 0x0000010C
#define PHY_SCL_START 0x00000100
#define PHY_SCL_CONFIG_1 0x00000118
#define PHY_SCL_CONFIG_2 0x0000011C
#define PHY_PAD_CTRL 0x00000120
#define PHY_DLL_RECALIB 0x00000124
#define PHY_DLL_ADRCTRL 0x00000128
#define PHY_LANE_SEL 0x0000012C
#define PHY_DLL_TRIM_1 0x00000130
#define PHY_DLL_TRIM_2 0x00000134
#define PHY_DLL_TRIM_3 0x00000138
#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
#define PHY_WRLVL_DYN_ODT 0x00000150
#define PHY_WRLVL_ON_OFF 0x00000154
#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
#define PHY_DLL_INCR_TRIM_1 0x00000164
#define PHY_DLL_INCR_TRIM_3 0x00000168
#define PHY_SCL_CONFIG_3 0x0000016C
#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
#define PHY_SCL_START_ADDR 0x00000188
#define PHY_DSCL_CNT 0x0000019C
#define PHY_DLL_TRIM_CLK 0x000001A4
#define PHY_DYNAMIC_BIT_LVL 0x000001AC
#define PHY_SCL_WINDOW_TRIM 0x000001B4
#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
#define PHY_SCL_CONFIG_4 0x000001BC
#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
#define PHY_VREF_TRAINING 0x000001C8
#define PHY_SCL_GATE_TIMING 0x000001E0
#endif /* _DDRPHY_LD20_REGS_H */
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