1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
|
/*
* (C) Copyright 2002
* Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* stuff specific for the sc520,
* but idependent of implementation */
#include <common.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
#include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* utility functions for boards based on the AMD sc520
*
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
*/
volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
int cpu_init_f(void)
{
/*
* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
writeb(0x07, &sc520_mmcr->uart1ctl);
writeb(0x07, &sc520_mmcr->uart2ctl);
/* first set the timer pin mapping */
writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
/* enable PCI bus arbiter (concurrent mode) */
writeb(0x02, &sc520_mmcr->sysarbctl);
/* enable external grants */
writeb(0x1f, &sc520_mmcr->sysarbmenb);
/* enable posted-writes */
writeb(0x04, &sc520_mmcr->hbctl);
if (CONFIG_SYS_SC520_HIGH_SPEED) {
/* set it to 133 MHz and write back */
writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
} else {
/* set it to 100 MHz and write back */
writeb(0x01, &sc520_mmcr->cpuctl);
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
/* wait at least one millisecond */
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
writeb(0x11, &sc520_mmcr->dbctl);
return x86_cpu_init_f();
}
unsigned long init_sc520_dram(void)
{
bd_t *bd = gd->bd;
u32 dram_present=0;
u32 dram_ctrl;
#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
* these refresh and delay values are better ? simply specified
* outright in the include/configs/{cfg} file since the HW designer
* simply dictates it.
*/
#else
u8 tmp;
u8 val;
int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
/* set SDRAM speed here */
refresh_rate /= 78;
if (refresh_rate <= 1) {
val = 0; /* 7.8us */
} else if (refresh_rate == 2) {
val = 1; /* 15.6us */
} else if (refresh_rate == 3 || refresh_rate == 4) {
val = 2; /* 31.2us */
} else {
val = 3; /* 62.4us */
}
tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
writeb(tmp, &sc520_mmcr->drcctl);
val = readb(&sc520_mmcr->drctmctl) & 0xf0;
if (cas_precharge_delay==3) {
val |= 0x04; /* 3T */
} else if (cas_precharge_delay==4) {
val |= 0x08; /* 4T */
} else if (cas_precharge_delay>4) {
val |= 0x0c;
}
if (ras_cas_delay > 3) {
val |= 2;
} else {
val |= 1;
}
writeb(val, &c520_mmcr->drctmctl);
#endif
/*
* We read-back the configuration of the dram
* controller that the assembly code wrote
*/
dram_ctrl = readl(&sc520_mmcr->drcbendadr);
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
/* bank 0 enabled */
dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
bd->bi_dram[0].size = bd->bi_dram[1].start;
} else {
bd->bi_dram[0].size = 0;
bd->bi_dram[1].start = bd->bi_dram[0].start;
}
if (dram_ctrl & 0x8000) {
/* bank 1 enabled */
dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
} else {
bd->bi_dram[1].size = 0;
bd->bi_dram[2].start = bd->bi_dram[1].start;
}
if (dram_ctrl & 0x800000) {
/* bank 2 enabled */
dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
} else {
bd->bi_dram[2].size = 0;
bd->bi_dram[3].start = bd->bi_dram[2].start;
}
if (dram_ctrl & 0x80000000) {
/* bank 3 enabled */
dram_present = (dram_ctrl & 0x7f000000) >> 2;
bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
} else {
bd->bi_dram[3].size = 0;
}
gd->ram_size = dram_present;
return dram_present;
}
#ifdef CONFIG_SYS_SC520_RESET
void reset_cpu(ulong addr)
{
printf("Resetting using SC520 MMCR\n");
/* Write a '1' to the SYS_RST of the RESCFG MMCR */
writeb(0x01, &sc520_mmcr->rescfg);
/* NOTREACHED */
}
#endif
|
