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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,luton";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <208333333>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x60000000 0x10200000>;
uart0: serial@10100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x10100000 0x20>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
gpio: pinctrl@70068 {
compatible = "mscc,luton-pinctrl";
reg = <0x70068 0x68>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 32>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
function = "sio";
};
uart_pins: uart-pins {
pins = "GPIO_30", "GPIO_31";
function = "uart";
};
};
sgpio: gpio@70130 {
compatible = "mscc,luton-sgpio";
status = "disabled";
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio_pins>;
pinctrl-names = "default";
reg = <0x0070130 0x100>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 64>;
};
spi0: spi-bitbang {
compatible = "mscc,luton-bb-spi";
status = "okay";
reg = <0x10000064 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
switch: switch@1010000 {
compatible = "mscc,vsc7527-switch";
reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
<0x1f0000 0x0100>, // VTSS_TO_DEV_1
<0x200000 0x0100>, // VTSS_TO_DEV_2
<0x210000 0x0100>, // VTSS_TO_DEV_3
<0x220000 0x0100>, // VTSS_TO_DEV_4
<0x230000 0x0100>, // VTSS_TO_DEV_5
<0x240000 0x0100>, // VTSS_TO_DEV_6
<0x250000 0x0100>, // VTSS_TO_DEV_7
<0x260000 0x0100>, // VTSS_TO_DEV_8
<0x270000 0x0100>, // VTSS_TO_DEV_9
<0x280000 0x0100>, // VTSS_TO_DEV_10
<0x290000 0x0100>, // VTSS_TO_DEV_11
<0x2a0000 0x0100>, // VTSS_TO_DEV_12
<0x2b0000 0x0100>, // VTSS_TO_DEV_13
<0x2c0000 0x0100>, // VTSS_TO_DEV_14
<0x2d0000 0x0100>, // VTSS_TO_DEV_15
<0x2e0000 0x0100>, // VTSS_TO_DEV_16
<0x2f0000 0x0100>, // VTSS_TO_DEV_17
<0x300000 0x0100>, // VTSS_TO_DEV_18
<0x310000 0x0100>, // VTSS_TO_DEV_19
<0x320000 0x0100>, // VTSS_TO_DEV_20
<0x330000 0x0100>, // VTSS_TO_DEV_21
<0x340000 0x0100>, // VTSS_TO_DEV_22
<0x350000 0x0100>, // VTSS_TO_DEV_23
<0x010000 0x1000>, // VTSS_TO_SYS
<0x020000 0x1000>, // VTSS_TO_ANA
<0x030000 0x1000>, // VTSS_TO_REW
<0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
<0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
<0x0a0000 0x0100>; // VTSS_TO_HSIO
reg-names = "port0", "port1", "port2", "port3",
"port4", "port5", "port6", "port7",
"port8", "port9", "port10", "port11",
"port12", "port13", "port14", "port15",
"port16", "port17", "port18", "port19",
"port20", "port21", "port22", "port23",
"sys", "ana", "rew", "gcb", "qs", "hsio";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
reg = <0>;
};
port1: port@1 {
reg = <1>;
};
port2: port@2 {
reg = <2>;
};
port3: port@3 {
reg = <3>;
};
port4: port@4 {
reg = <4>;
};
port5: port@5 {
reg = <5>;
};
port6: port@6 {
reg = <6>;
};
port7: port@7 {
reg = <7>;
};
port8: port@8 {
reg = <8>;
};
port9: port@9 {
reg = <9>;
};
port10: port@10 {
reg = <10>;
};
port11: port@11 {
reg = <11>;
};
port12: port@12 {
reg = <12>;
};
port13: port@13 {
reg = <13>;
};
port14: port@14 {
reg = <14>;
};
port15: port@15 {
reg = <15>;
};
port16: port@16 {
reg = <16>;
};
port17: port@17 {
reg = <17>;
};
port18: port@18 {
reg = <18>;
};
port19: port@19 {
reg = <19>;
};
port20: port@20 {
reg = <20>;
};
port21: port@21 {
reg = <21>;
};
port22: port@22 {
reg = <22>;
};
port23: port@23 {
reg = <23>;
};
};
};
mdio0: mdio@700a0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,luton-miim";
reg = <0x700a0 0x24>;
status = "disabled";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
phy6: ethernet-phy@6 {
reg = <6>;
};
phy7: ethernet-phy@7 {
reg = <7>;
};
phy8: ethernet-phy@8 {
reg = <8>;
};
phy9: ethernet-phy@9 {
reg = <9>;
};
phy10: ethernet-phy@10 {
reg = <10>;
};
phy11: ethernet-phy@11 {
reg = <11>;
};
};
};
};
|
