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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,ocelot";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller@0 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x70000000 0x2000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@0 {
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x0 0x2c>;
};
intc: interrupt-controller@70 {
compatible = "mscc,ocelot-icpu-intr";
reg = <0x70 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;
reg-io-width = <4>;
reg-shift = <2>;
spi-max-frequency = <18000000>; /* input clock */
clocks = <&ahb_clk>;
status = "disabled";
};
switch: switch@1010000 {
pinctrl-0 = <&miim1_pins>;
pinctrl-names = "default";
compatible = "mscc,vsc7514-switch";
reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
<0x11f0000 0x100>, // VTSS_TO_DEV_1
<0x1200000 0x100>, // VTSS_TO_DEV_2
<0x1210000 0x100>, // VTSS_TO_DEV_3
<0x1220000 0x100>, // VTSS_TO_DEV_4
<0x1230000 0x100>, // VTSS_TO_DEV_5
<0x1240000 0x100>, // VTSS_TO_DEV_6
<0x1250000 0x100>, // VTSS_TO_DEV_7
<0x1260000 0x100>, // VTSS_TO_DEV_8
<0x1270000 0x100>, // VTSS_TO_DEV_9
<0x1280000 0x100>, // VTSS_TO_DEV_10
<0x1010000 0x10000>, // VTSS_TO_SYS
<0x1030000 0x10000>, // VTSS_TO_REW
<0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
<0x10d0000 0x10000>, // VTSS_TO_HSIO
<0x1800000 0x80000>,// VTSS_TO_QSYS
<0x1880000 0x10000>;// VTSS_TO_ANA
reg-names = "port0", "port1", "port2", "port3", "port4",
"port5", "port6", "port7", "port8", "port9",
"port10",
"sys", "rew", "qs", "hsio", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio0: mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x24>;
interrupts = <14>;
status = "disabled";
};
mdio1: mdio@10700f0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x10700c0 0x24>;
interrupts = <14>;
status = "disabled";
};
hsio: syscon@10d0000 {
compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
reg = <0x10d0000 0x10000>;
serdes_hsio: serdes_hsio {
compatible = "mscc,vsc7514-serdes";
#phy-cells = <3>;
};
};
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
};
gpio: pinctrl@1070034 {
compatible = "mscc,ocelot-pinctrl";
reg = <0x1070034 0x68>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
function = "sg0";
};
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
spi_cs1_pin: spi-cs1-pin {
pins = "GPIO_8";
function = "si";
};
miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
};
spi_cs2_pin: spi-cs2-pin {
pins = "GPIO_9";
function = "si";
};
spi_cs3_pin: spi-cs3-pin {
pins = "GPIO_16";
function = "si";
};
spi_cs4_pin: spi-cs4-pin {
pins = "GPIO_17";
function = "si";
};
};
sgpio: gpio@10700f8 {
compatible = "mscc,ocelot-sgpio";
status = "disabled";
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio_pins>;
pinctrl-names = "default";
reg = <0x10700f8 0x100>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 64>;
};
};
};
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