summaryrefslogtreecommitdiff
path: root/arch/mips/dts/pic32mzda.dtsi
blob: 8aff9eb8125f4e76464be8a662be8ac938e48cb5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Microchip Technology, Inc.
 * Purna Chandra Mandal, <purna.mandal@microchip.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/microchip,clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"

/ {
	compatible = "microchip,pic32mzda", "microchip,pic32mz";

	aliases {
		gpio0 = &gpioA;
		gpio1 = &gpioB;
		gpio2 = &gpioC;
		gpio3 = &gpioD;
		gpio4 = &gpioE;
		gpio5 = &gpioF;
		gpio6 = &gpioG;
		gpio7 = &gpioH;
		gpio8 = &gpioJ;
		gpio9 = &gpioK;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "mips,mips14kc";
			device-type = "cpu";
			reg = <0>;
		};
	};

	clock: clk@1f801200 {
		compatible = "microchip,pic32mzda-clk";
		reg = <0x1f801200 0x1000>;
		#clock-cells = <1>;
	};

	uart1: serial@1f822000 {
		compatible = "microchip,pic32mzda-uart";
		reg = <0x1f822000 0x50>;
		interrupt-parent = <&evic>;
		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
		clocks = <&clock PB2CLK>;
	};

	uart2: serial@1f822200 {
		compatible = "microchip,pic32mzda-uart";
		reg = <0x1f822200 0x50>;
		interrupt-parent = <&evic>;
		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock PB2CLK>;
		status = "disabled";
	};

	uart6: serial@1f822a00 {
		compatible = "microchip,pic32mzda-uart";
		reg = <0x1f822a00 0x50>;
		interrupt-parent = <&evic>;
		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock PB2CLK>;
		status = "disabled";
	};

	evic: interrupt-controller@1f810000 {
		compatible = "microchip,pic32mzda-evic";
		interrupt-controller;
		#interrupt-cells = <2>;
		reg = <0x1f810000 0x1000>;
	};

	pinctrl: pinctrl@1f801400 {
		compatible = "microchip,pic32mzda-pinctrl";
		reg = <0x1f801400 0x100>, /* in  */
		      <0x1f801500 0x200>, /* out */
		      <0x1f860000 0xa00>; /* port */
		reg-names = "ppsin","ppsout","port";
		status = "disabled";

		ranges = <0 0x1f860000 0xa00>;
		#address-cells = <1>;
		#size-cells = <1>;
		gpioA: gpio0@0 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x000 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioB: gpio1@100 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x100 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioC: gpio2@200 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x200 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioD: gpio3@300 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x300 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioE: gpio4@400 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x400 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioF: gpio5@500 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x500 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioG: gpio6@600 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x600 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioH: gpio7@700 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x700 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioJ: gpio8@800 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x800 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpioK: gpio9@900 {
			compatible = "microchip,pic32mzda-gpio";
			reg = <0x900 0x48>;
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	sdhci: sdhci@1f8ec000 {
		compatible = "microchip,pic32mzda-sdhci";
		reg = <0x1f8ec000 0x100>;
		interrupt-parent = <&evic>;
		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock REF4CLK>, <&clock PB5CLK>;
		clock-names = "base_clk", "sys_clk";
		clock-freq-min-max = <25000000>,<25000000>;
		bus-width = <4>;
		status = "disabled";
	};

	ethernet: ethernet@1f882000 {
		compatible = "microchip,pic32mzda-eth";
		reg = <0x1f882000 0x1000>;
		interrupt-parent = <&evic>;
		interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock PB5CLK>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	usb: musb@1f8e3000 {
		compatible = "microchip,pic32mzda-usb";
		reg = <0x1f8e3000 0x1000>,
		      <0x1f884000 0x1000>;
		reg-names = "mc", "control";
		interrupt-parent = <&evic>;
		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
			     <133 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock PB5CLK>;
		clock-names = "usb_clk";
		status = "disabled";
	};
};