1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T104X Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e5500_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
#cooling-cells = <2>;
};
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
#cooling-cells = <2>;
};
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
#cooling-cells = <2>;
};
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
#cooling-cells = <2>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
usb0@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;
phy_type = "utmi";
};
usb1@211000 {
compatible = "fsl-usb2-dr";
reg = <0x211000 0x1000>;
phy_type = "utmi";
};
sata: sata@220000 {
compatible = "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
sata-offset = <0x1000>;
sata-number = <2>;
sata-fpdma = <0>;
};
esdhc: esdhc@114000 {
compatible = "fsl,esdhc";
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe250000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe260000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe270000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
law_trgt_if = <3>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
};
};
|
