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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T4240 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e6500_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
fsl,portid-mapping = <0x80000000>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
fsl,portid-mapping = <0x80000000>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
fsl,portid-mapping = <0x80000000>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
fsl,portid-mapping = <0x80000000>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
fsl,portid-mapping = <0x80000000>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
fsl,portid-mapping = <0x80000000>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
fsl,portid-mapping = <0x80000000>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
fsl,portid-mapping = <0x80000000>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
fsl,portid-mapping = <0x80000000>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
};
};
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