blob: ae5c60716ffdd82742dc783095eebd54a0dde7eb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <common.h>
void invalidate_icache_all(void)
{
asm volatile ("fence.i" ::: "memory");
}
void flush_dcache_all(void)
{
asm volatile ("fence" :::"memory");
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
* instruction cache. Invalidate all of it instead.
*/
invalidate_icache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void cache_flush(void)
{
invalidate_icache_all();
flush_dcache_all();
}
void flush_cache(unsigned long addr, unsigned long size)
{
invalidate_icache_all();
flush_dcache_all();
}
__weak void icache_enable(void)
{
}
__weak void icache_disable(void)
{
}
__weak int icache_status(void)
{
return 0;
}
__weak void dcache_enable(void)
{
}
__weak void dcache_disable(void)
{
}
__weak int dcache_status(void)
{
return 0;
}
|
