1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
|
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#define DATARATE_800MHZ 800000000
#define DATARATE_900MHZ 900000000
#define DATARATE_1000MHZ 1000000000
#define DATARATE_1200MHZ 1200000000
#define DATARATE_1300MHZ 1300000000
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};
|
