1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <malloc.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
{
int phy_reg;
u32 phy_id;
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
phy_id = (phy_reg & 0xffff) << 16;
phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
phy_id |= (phy_reg & 0xffff);
if (phy_id == PHY_UID_IN112525_S03)
return true;
else
return false;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
struct memac_mdio_info mdio_info;
struct memac_mdio_controller *reg;
int i, interface;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
switch (srds_s1) {
case 19:
wriop_set_phy_address(WRIOP1_DPMAC2, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
AQR107_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
AQR107_PHY_ADDR2);
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
INPHI_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
INPHI_PHY_ADDR1);
}
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
RGMII_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
RGMII_PHY_ADDR2);
break;
case 18:
wriop_set_phy_address(WRIOP1_DPMAC7, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC8, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC9, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC10, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
AQR107_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
AQR107_PHY_ADDR2);
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
INPHI_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
INPHI_PHY_ADDR1);
}
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
RGMII_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
RGMII_PHY_ADDR2);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
srds_s1);
goto next;
}
for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_25G_AUI:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_XLAUI:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
next:
cpu_eth_init(bis);
#endif /* CONFIG_FSL_MC_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
* upload application
*/
gd->jt->strcpy = strcpy;
gd->jt->mdelay = mdelay;
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
gd->jt->phy_find_by_mask = phy_find_by_mask;
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
#if defined(CONFIG_FSL_MC_ENET)
mc_env_boot();
#endif
}
#endif /* CONFIG_RESET_PHY_R */
int fdt_fixup_board_phy(void *fdt)
{
int mdio_offset;
int ret;
struct mii_dev *dev;
ret = 0;
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
if (mdio_offset < 0)
mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
if (mdio_offset < 0) {
printf("mdio@0x8B9700 node not found in dts\n");
return mdio_offset;
}
ret = fdt_setprop_string(fdt, mdio_offset, "status",
"disabled");
if (ret) {
printf("Could not set disable mdio@0x8B97000 %s\n",
fdt_strerror(ret));
return ret;
}
}
return ret;
}
|
