1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*
* For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
* tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
* all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
* For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
* from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
*
* CPO value doesn't matter if workaround for errata 111 and 134 enabled.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{2, 333, 8, 7, 5, 0},
{2, 400, 8, 9, 5, 0},
{2, 549, 8, 11, 5, 0},
{2, 680, 8, 10, 5, 0},
{2, 850, 8, 12, 5, 1},
{1, 333, 6, 7, 3, 0},
{1, 400, 6, 9, 3, 0},
{1, 549, 6, 11, 3, 0},
{1, 680, 1, 10, 5, 0},
{1, 850, 1, 12, 5, 0},
{}
};
static const struct board_specific_parameters udimm1[] = {
/*
* memory controller 1
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{2, 333, 8, 7, 5, 0},
{2, 400, 8, 9, 5, 0},
{2, 549, 8, 11, 5, 0},
{2, 680, 8, 11, 5, 0},
{2, 850, 8, 13, 5, 1},
{1, 333, 6, 7, 3, 0},
{1, 400, 6, 9, 3, 0},
{1, 549, 6, 11, 3, 0},
{1, 680, 1, 11, 6, 0},
{1, 850, 1, 13, 6, 0},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
udimm1,
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{2, 333, 4, 7, 3, 0},
{2, 400, 4, 9, 3, 0},
{2, 549, 4, 11, 3, 0},
{2, 680, 4, 10, 3, 0},
{2, 850, 4, 12, 3, 1},
{}
};
static const struct board_specific_parameters rdimm1[] = {
/*
* memory controller 1
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{2, 333, 4, 7, 3, 0},
{2, 400, 4, 9, 3, 0},
{2, 549, 4, 11, 3, 0},
{2, 680, 4, 11, 3, 0},
{2, 850, 4, 13, 3, 1},
{}
};
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
rdimm1,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 1) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
if (popts->registered_dimm_en)
pbsp = rdimms[ctrl_num];
else
pbsp = udimms[ctrl_num];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->write_data_delay = pbsp->write_data_delay;
popts->twot_en = pbsp->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
}
|
