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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# (C) Copyright 2011
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
# bit 3-0: MPPSel0 2, NF_IO[2]
# bit 7-4: MPPSel1 2, NF_IO[3]
# bit 12-8: MPPSel2 2, NF_IO[4]
# bit 15-12: MPPSel3 2, NF_IO[5]
# bit 19-16: MPPSel4 1, NF_IO[6]
# bit 23-20: MPPSel5 1, NF_IO[7]
# bit 27-24: MPPSel6 1, SYSRST_O
# bit 31-28: MPPSel7 0, GPO[7]
DATA 0xFFD10004 0x03303300
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
# bit 3-0: MPPSel16 0, GPIO[16]
# bit 7-4: MPPSel17 0, GPIO[17]
# bit 12-8: MPPSel18 1, NF_IO[0]
# bit 15-12: MPPSel19 1, NF_IO[1]
# bit 19-16: MPPSel20 0, GPIO[20]
# bit 23-20: MPPSel21 0, GPIO[21]
# bit 27-24: MPPSel22 0, GPIO[22]
# bit 31-28: MPPSel23 0, GPIO[23]
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
#Dram initalization
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
# bit13-0: 0x4E0 (DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
# bit 3-0: 0 reserved
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x00000001 # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 00, Cs0size=2Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000652 # DDR Mode
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strenght reduced
# bit2: 1, DDR ODT control lsd disabled
# bit5-3: 000, required
# bit6: 0, DDR ODT control msb disabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add a sample stage
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
# bit3-0 : 0000, required
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
# bit15-12: 0100, internal ODT assertion 4 cycles after read
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
# bit31-20: 0 , required
DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
# bit3-0 : 0001, M_ODT assertion same cycle as write
# bit7-4 : 0101, M_ODT de-assertion x cycles after write
# bit11-8 : 0100, internal ODT assertion x cycles after write
# bit15-12: 1000, internal ODT de-assertion x cycles after write
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 00, ODT1 controlled by register
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
# bit14 :1, STARTBURST ODT enabled
# bit15 :1, Use ODT Block
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
# bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0
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