blob: 3fdfb47ab235b4d41e1559de6f2c48098a110500 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2012 Freescale Semiconductor, Inc.
# Refer docs/README.pblimage for more details about how-to configure
# and create PBL boot image
#
#PBI commands
#Configure ALTCBAR for DCSR -> DCSR@89000000
091380c0 000009C4
09000010 00000000
091380c0 000009C4
09000014 00000000
091380c0 000009C4
09000018 81d00000
#Workaround for A-004849
091380c0 000009C4
890B0050 00000002
091380c0 000009C4
890B0054 00000002
091380c0 000009C4
890B0058 00000002
091380c0 000009C4
890B005C 00000002
091380c0 000009C4
890B0090 00000002
091380c0 000009C4
890B0094 00000002
091380c0 000009C4
890B0098 00000002
091380c0 000009C4
890B009C 00000002
091380c0 000009C4
890B0108 00000012
091380c0 000009C4
#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
89021008 0000f000
091380c0 000009C4
89021028 0000f000
091380c0 000009C4
89021048 0000f000
091380c0 000009C4
89021068 0000f000
091380c0 000009C4
#Flush PBL data
09138000 00000000
#Disable ALTCBAR
09000018 00000000
091380c0 000009C4
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
091380c0 00000100
09010100 00000000
09010104 fff0000b
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff00000
09000d08 81000013
09000010 00000000
09000014 ff000000
09000018 81000000
#Initialize eSPI controller, default configuration is slow for eSPI to
#load data, this configuration comes from u-boot eSPI driver.
09110000 80000403
09110020 27170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
09138000 00000000
091380c0 00000000
|
