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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2013 Seco USA Inc
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* DDR IO TYPE */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* DATA STROBE */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
/* DATA */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
/* ADDRESS */
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
/* CONTROL */
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
/* CLOCK */
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
/*
* DDR3 SETTINGS
* Read Data Bit Delay
*/
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
/* Write Leveling */
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
/* DQS gating, read delay, write delay calibration values */
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
/* Read calibration */
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
/* write calibration */
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
/* Complete calibration by forced measurement: */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/*
* MMDC init:
* in DDR3, 64-bit mode, only MMDC0 is init
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
/* Initialize DDR3 on CS_0 and CS_1 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
/* P0 01c */
/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
/*ZQ - Calibrationi */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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