1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
|
/*
* K2E EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
switch (clk) {
case sys_clk:
clk_freq = 100000000;
break;
case alt_core_clk:
clk_freq = 100000000;
break;
case pa_clk:
clk_freq = 100000000;
break;
case ddr3a_clk:
clk_freq = 100000000;
break;
default:
clk_freq = 0;
break;
}
return clk_freq;
}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_800,
[SPD850] = CORE_PLL_850,
[SPD1000] = CORE_PLL_1000,
[SPD1250] = CORE_PLL_1250,
[SPD1350] = CORE_PLL_1350,
[SPD1400] = CORE_PLL_1400,
[SPD1500] = CORE_PLL_1500,
};
/* DEV and ARM speed definitions as specified in DEVSPEED register */
int speeds[DEVSPEED_NUMSPDS] = {
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800,
};
s16 divn_val[16] = {
0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
struct pll_init_data *data;
switch (pll) {
case MAIN_PLL:
speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case PASS_PLL:
data = &pa_pll_config;
break;
default:
data = NULL;
}
return data;
}
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2E_EMAC0",
.rx_flow = 0,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC1",
.rx_flow = 8,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC2",
.rx_flow = 16,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC3",
.rx_flow = 24,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC4",
.rx_flow = 32,
.phy_addr = 4,
.slave_port = 5,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC5",
.rx_flow = 40,
.phy_addr = 5,
.slave_port = 6,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC6",
.rx_flow = 48,
.phy_addr = 6,
.slave_port = 7,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2E_EMAC7",
.rx_flow = 56,
.phy_addr = 7,
.slave_port = 8,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
{
if (!strcmp(name, "keystone-k2e-evm"))
return 0;
return -1;
}
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls();
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif
|
