1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
|
/*
* (C) Copyright 2011
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
*
* (C) Copyright 2015
* Kamil Lulko, <rev13@wp.pl>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
};
struct stm32_gpio_regs {
u32 moder; /* GPIO port mode */
u32 otyper; /* GPIO port output type */
u32 ospeedr; /* GPIO port output speed */
u32 pupdr; /* GPIO port pull-up/pull-down */
u32 idr; /* GPIO port input data */
u32 odr; /* GPIO port output data */
u32 bsrr; /* GPIO port bit set/reset */
u32 lckr; /* GPIO port configuration lock */
u32 afr[2]; /* GPIO alternate function */
};
#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
x->pupd > 2 || x->speed > 3)
int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
const struct stm32_gpio_ctl *ctl)
{
struct stm32_gpio_regs *gpio_regs;
u32 i;
int rv;
if (CHECK_DSC(dsc)) {
rv = -EINVAL;
goto out;
}
if (CHECK_CTL(ctl)) {
rv = -EINVAL;
goto out;
}
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
i = (dsc->pin & 0x07) * 4;
clrbits_le32(&gpio_regs->afr[dsc->pin >> 3], (0xF << i));
setbits_le32(&gpio_regs->afr[dsc->pin >> 3], ctl->af << i);
i = dsc->pin * 2;
clrbits_le32(&gpio_regs->moder, (0x3 << i));
setbits_le32(&gpio_regs->moder, ctl->mode << i);
clrbits_le32(&gpio_regs->otyper, (0x3 << i));
setbits_le32(&gpio_regs->otyper, ctl->otype << i);
clrbits_le32(&gpio_regs->ospeedr, (0x3 << i));
setbits_le32(&gpio_regs->ospeedr, ctl->speed << i);
clrbits_le32(&gpio_regs->pupdr, (0x3 << i));
setbits_le32(&gpio_regs->pupdr, ctl->pupd << i);
rv = 0;
out:
return rv;
}
int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
{
struct stm32_gpio_regs *gpio_regs;
int rv;
if (CHECK_DSC(dsc)) {
rv = -EINVAL;
goto out;
}
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
if (state)
writel(1 << dsc->pin, &gpio_regs->bsrr);
else
writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
rv = 0;
out:
return rv;
}
int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
{
struct stm32_gpio_regs *gpio_regs;
int rv;
if (CHECK_DSC(dsc)) {
rv = -EINVAL;
goto out;
}
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
out:
return rv;
}
/* Common GPIO API */
int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
int gpio_free(unsigned gpio)
{
return 0;
}
int gpio_direction_input(unsigned gpio)
{
struct stm32_gpio_dsc dsc;
struct stm32_gpio_ctl ctl;
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
return stm32_gpio_config(&dsc, &ctl);
}
int gpio_direction_output(unsigned gpio, int value)
{
struct stm32_gpio_dsc dsc;
struct stm32_gpio_ctl ctl;
int res;
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_OUT;
ctl.otype = STM32_GPIO_OTYPE_PP;
ctl.pupd = STM32_GPIO_PUPD_NO;
ctl.speed = STM32_GPIO_SPEED_50M;
res = stm32_gpio_config(&dsc, &ctl);
if (res < 0)
goto out;
res = stm32_gpout_set(&dsc, value);
out:
return res;
}
int gpio_get_value(unsigned gpio)
{
struct stm32_gpio_dsc dsc;
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
return stm32_gpin_get(&dsc);
}
int gpio_set_value(unsigned gpio, int value)
{
struct stm32_gpio_dsc dsc;
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
return stm32_gpout_set(&dsc, value);
}
|
