1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
/*
* Copyright (c) 2016 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
struct rk_pwm_priv {
struct rk3288_pwm *regs;
ulong freq;
uint enable_conf;
};
static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
if (polarity)
priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
else
priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
return 0;
}
static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
uint duty_ns)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
struct rk3288_pwm *regs = priv->regs;
unsigned long period, duty;
debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
PWM_CONTINUOUS | priv->enable_conf |
RK_PWM_DISABLE,
®s->ctrl);
period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
writel(period, ®s->period_hpr);
writel(duty, ®s->duty_lpr);
debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
return 0;
}
static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
struct rk3288_pwm *regs = priv->regs;
debug("%s: Enable '%s'\n", __func__, dev->name);
clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
return 0;
}
static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
return 0;
}
static int rk_pwm_probe(struct udevice *dev)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
struct clk clk;
int ret = 0;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0) {
debug("%s get clock fail!\n", __func__);
return -EINVAL;
}
priv->freq = clk_get_rate(&clk);
priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
return 0;
}
static const struct pwm_ops rk_pwm_ops = {
.set_invert = rk_pwm_set_invert,
.set_config = rk_pwm_set_config,
.set_enable = rk_pwm_set_enable,
};
static const struct udevice_id rk_pwm_ids[] = {
{ .compatible = "rockchip,rk3288-pwm" },
{ }
};
U_BOOT_DRIVER(rk_pwm) = {
.name = "rk_pwm",
.id = UCLASS_PWM,
.of_match = rk_pwm_ids,
.ops = &rk_pwm_ops,
.ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
.probe = rk_pwm_probe,
.priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
};
|
