blob: f93ffa8d9f8ed453be8edcaba5aa0f451c54c4fd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>.
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*/
#include <common.h>
#include <asm/io.h>
#include <usb.h>
#include "ehci.h"
#include <asm/arch/hardware.h>
#include <asm/arch/spr_misc.h>
static void spear6xx_usbh_stop(void)
{
struct misc_regs *const misc_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 periph1_rst = readl(misc_p->periph1_rst);
periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2;
writel(periph1_rst, misc_p->periph1_rst);
udelay(1000);
periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2);
writel(periph1_rst, misc_p->periph1_rst);
}
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u32 ehci = 0;
switch (index) {
case 0:
ehci = CONFIG_SYS_UHC0_EHCI_BASE;
break;
case 1:
ehci = CONFIG_SYS_UHC1_EHCI_BASE;
break;
default:
printf("ERROR: wrong controller index!\n");
break;
};
*hccr = (struct ehci_hccr *)(ehci + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
(uint32_t)*hccr, (uint32_t)*hcor,
(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
/*
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
int ehci_hcd_stop(int index)
{
#if defined(CONFIG_SPEAR600)
spear6xx_usbh_stop();
#endif
return 0;
}
|
