blob: ec4284216f9f0c550248d989fdcb30155dafc1b5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Freescale MCF54451 EVB board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M54451EVB_H
#define _M54451EVB_H
#include <linux/stringify.h>
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_M54451EVB /* M54451EVB board */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
#undef CONFIG_WATCHDOG
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/* Network configuration */
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_ETHPRIME "FEC0"
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_HOSTNAME "M54451EVB"
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
"save\0" \
""
#else
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#endif
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
/* Timer */
#define CONFIG_MCFTMR
/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_PRAM 2048 /* 2048 KB */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
#define CONFIG_SYS_SDRAM_CFG2 0x57670000
#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD 0x80810000
#define CONFIG_SYS_SDRAM_MODE 0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
#ifdef CONFIG_CF_SBF
# define CONFIG_SERIAL_BOOT
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is not embedded in u-boot. First time runing may have env
* crc error warning if there is no correct environment on the flash.
*/
#undef CONFIG_ENV_OVERWRITE
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_CHECKSUM
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
#endif
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CONFIG_CMD_JFFS2
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* CS0 - NOR Flash 16MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
/* Flash */
#define CONFIG_SYS_CS0_BASE 0x00000000
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00004D80
#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
#endif /* _M54451EVB_H */
|
