blob: cfe8d8cbedecfea3e50ce6d3226fd62837215a53 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2013-2016, NVIDIA CORPORATION.
*/
#ifndef _P2771_0000_H
#define _P2771_0000_H
#include <linux/sizes.h>
#include "tegra186-common.h"
/* High-level configuration options */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* PCI host support */
#define BOARD_EXTRA_ENV_SETTINGS \
"calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
"ramdisk_addr_r\0" \
"kernel_addr_r_align=00200000\0" \
"kernel_addr_r_offset=00080000\0" \
"kernel_addr_r_size=02000000\0" \
"kernel_addr_r_aliases=loadaddr\0" \
"fdt_addr_r_align=00200000\0" \
"fdt_addr_r_offset=00000000\0" \
"fdt_addr_r_size=00200000\0" \
"scriptaddr_align=00200000\0" \
"scriptaddr_offset=00000000\0" \
"scriptaddr_size=00200000\0" \
"pxefile_addr_r_align=00200000\0" \
"pxefile_addr_r_offset=00000000\0" \
"pxefile_addr_r_size=00200000\0" \
"ramdisk_addr_r_align=00200000\0" \
"ramdisk_addr_r_offset=00000000\0" \
"ramdisk_addr_r_size=02000000\0"
#include "tegra-common-post.h"
/* Crystal is 38.4MHz. clk_m runs at half that rate */
#define COUNTER_FREQUENCY 19200000
#endif
|
