blob: d566fe5a2f3d80c741eeb3faea865196548728dc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
|
/*
* (c) 2011 Graf-Syteco, Matthias Weisser
* <weisserm@arcor.de>
*
* Configuation settings for the zmx25 board
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
/*
* Environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"gs_fast_boot=setenv bootdelay 5\0" \
"gs_slow_boot=setenv bootdelay 10\0" \
"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
"bootm 0x81000000; bootelf 0x81000000\0"
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Hardware drivers
*/
/*
* GPIO
*/
#define CONFIG_MXC_GPIO
/*
* Serial
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
/*
* Ethernet
*/
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x00
#define CONFIG_MII
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
/*
* Additional command
*/
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE 0xA0000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (128 * 1024)
/*
* CFI FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PREBOOT ""
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
#endif /* __CONFIG_H */
|
