blob: c4587a1837c81a41b52e644c54958301ffbb1ca8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013 - 2017 Xilinx.
*
* Configuration settings for the Xilinx Zynq CSE board.
* See zynq-common.h for Zynq common configs
*/
#ifndef __CONFIG_ZYNQ_CSE_H
#define __CONFIG_ZYNQ_CSE_H
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF
#include <configs/zynq-common.h>
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#undef CONFIG_SYS_CBSIZE
#undef CONFIG_BOOTM_VXWORKS
#undef CONFIG_BOOTM_LINUX
#define CONFIG_SYS_CBSIZE 1024
#undef CONFIG_SYS_INIT_RAM_ADDR
#undef CONFIG_SYS_INIT_RAM_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#undef CONFIG_SPL_BSS_START_ADDR
#undef CONFIG_SPL_BSS_MAX_SIZE
#define CONFIG_SPL_BSS_START_ADDR 0x20000
#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
#endif /* __CONFIG_ZYNQ_CSE_H */
|
