blob: 8ad8eaedfde4a597dbaf9360a28a7e441b0661dd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2018 Angelo Dureghello <angelo@sysam.it>
*/
#ifndef __spi_coldfire_h
#define __spi_coldfire_h
#define MAX_CTAR_REGS 8
#define MAX_CTAR_FIELDS 8
/*
* struct coldfire_spi_platdata - information about a coldfire spi module
*
* @regs_addr: base address for module registers
* @speed_hz: default SCK frequency
* @mode: default SPI mode
* @num_cs: number of DSPI chipselect signals
*/
struct coldfire_spi_platdata {
fdt_addr_t regs_addr;
uint speed_hz;
uint mode;
uint num_cs;
uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
};
#endif /* __spi_coldfire_h */
|
